Lecture Notes in Computer Science 4917

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112 T.-C. Chiueh Despite its robustness advantage, most real-world programs do not incorporate array bounds checking, because its performance penalty is too high to be considered practical. Whereas almost all previous research in this area focused on static analysis techniques to reduce redundant bounds checks and thus minimize the checking overhead, this work took a completely different approach that relies on the debug register hardware feature available in most mainstream CPUs. By leveraging debug registers’ address monitoring capability, Boud can accurately detect array bound violations almost for free, i.e., without incurring any perarray-reference overhead most of the time. We have successfully built a Boud prototype based on the bound-checking GCC compiler under Red Hat Linux 7.2. The current Boud prototype can check bound violations for array references both within and outside loops, although it applies debug register-based bounds checking only to within-loop array references. Performance measurements collected from running a set network applications on the Boud prototype demonstrate that the throughput and latency penalty of Boud’s array bounds checking mechanism is below 7.7% and 8.8%, respectively, when compared with the vanilla GCC compiler, which does not perform any bounds checking. This puts Boud as one of the fastest array bounds checking compilers ever reported in the literature for C programs on the X86 architecture. References 1. Perens, B.: Electric fence: a malloc() debugger for linux and unix. http://perens.com/FreeSoftware/ 2. Bentley, C., Watterson, S.A., Lowenthal, D.K.: A comparison of array bounds checking on superscalar and vliw architectures. In: The annual IEEE Workshop on Workload Characterization (submitted) 3. Lam, L.-C., Chiueh, T.-C.: Checking array bound violation using segmentation hardware. In: DSN 2005. Proceedings of 2005 International Conference on Dependable Systems and Networks (June 2005) 4. Cowan, C., et al.: Stackguard: Automatic adaptive detection and prevention of buffer-overflow attacks. In: Proc. 7th USENIX Security Conference, San Antonio, Texas, pp. 63–78 (January 1998) 5. GCC. Bounds-checking gcc, http://www.gnu.org/software/gcc/projects /bp/ main.html 6. Pearson, G.: Array bounds checking with turbo c. Dr. Dobb’s Journal of Software Tools 16(5) 72, 74, 78–79, 81–82, 104–107 (1991) 7. Patil, H., Fischer, C.N.: Efficient run-time monitoring using shadow processing. In: Proceedings of Automated and Algorithmic Debugging Workshop, pp. 119–132 (1995) 8. Xi, H., Pfenning, F.: Eliminating array bound checking through dependent types. In: SIGPLAN Conference on Programming Language Design and Implementation, pp. 249–257 (1998) 9. Xi, H., Xia, S.: Towards array bound check elimination in java virtual machine language. In: Proceedings of CASCON 1999, Mississauga, Ontario, pp. 110–125 (November 1999) 10. Intel. IA-32 Intel Architecture Software Developer’s Manual vol. 2 Instruction Set Reference, http://www.intel.com/design/Pentium4/manuals/
Fast Bounds Checking Using Debug Register 113 11. Intel. Ia-32 intel architecture software developer’s manual. volume 3: System programming guide, http://developer.intel.com/design/pentium4/manuals/245472.htm 12. Asuru, J.M.: Optimization of array subscript range checks. ACM letters on Programming Languages and Systems 1(2), 109–118 (1992) 13. Jones, R.W.M., Kelly, P.H.J.: Backwards-compatible bounds checking for arrays and pointers in c programs. In: Proceedings of Automated and Algorithmic Debugging Workshop, pp. 13–26 (1997) 14. Kolte, P., Wolfe, M.: Elimination of redundant array subscript range checks. In: SIGPLAN Conference on Programming Language Design and Implementation, pp. 270–278 (1995) 15. Prasad, M., Chiueh, T.-C.: A binary rewriting approach to stack-based buffer overflow attacks. In: Proceedings of 2003 USENIX Conference (June 2003) 16. Qin, F., Lu, S., Zhou, Y.: Safemem: Exploiting ecc-memory for detecting memory leaks and memory corruption during production runs. In: HPCA 2005. Proceedings of the 11th International Symposium on High-Performance Computer Architecture (February 2005) 17. Gupta, R.: A fresh look at optimizing array bound checking. In: SIGPLAN Conference on Programming Language Design and Implementation, pp. 272–282 (1990) 18. Gupta, R.: Optimizing array bound checks using flow analysis. ACM Letters on Programming Languages and Systems 2(1-4), 135–150 (1993) 19. Bodik, R., Gupta, R., Sarkar, V.: Abcd: eliminating array bounds checks on demand. In: SIGPLAN Conference on Programming Language Design and Implementation, pp. 321–333 (2000) 20. Chiueh, T.-C., Hsu, F.-H.: Rad: A compiler time solution to buffer overflow attacks. In: ICDCS. Proceedings of International Conference on Distributed Computing Systems, Phoenix, Arizona (April 2001) 21. Chiueh, T.-C., Venkitachalam, G., Pradhan, P.: Integrating segmentation and paging protection for safe, efficient and transparent software extensions. In: Proceedings of 17th ACM Symposium on Operating Systems Principles, Charleston, SC (December 1999)
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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BRAM-LUT Tradeoff on a Polymorphic
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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speed-up 8 6 4 2 0 FFT3D 256 64-A F
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Normalized Cycle Count 1.00 0.90 0.
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Integrated CPU Cache Power Manageme
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Variation-Aware Software Techniques
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Average leakage-power saving (%) Va
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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Turbo-ROB: A Low Cost Checkpoint/Re
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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266 P. Akl and A. Moshovos throttli
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268 P. Akl and A. Moshovos 80% 70%
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270 P. Akl and A. Moshovos 25% 20%
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272 P. Akl and A. Moshovos [4] Burg
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274 A. García et al. execution tim
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276 A. García et al. whenever LPA
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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Complementing Missing and Inaccurat
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Using Dynamic Binary Instrumentatio
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L1 D-Cache Miss Rate (%) CPI 5 4 3
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CPI Error (%) 10 5 0 -5 -10 FP Resu
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Compiler Techniques for Reducing Da
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References Compiler Techniques for
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Code Arrangement of Embedded Java V
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Aggressive Function Inlining: Preve
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400 Author Index Shajrawi, Yousef 3
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