Lecture Notes in Computer Science 4917

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308 V.M. Weaver and S.A. McKee L1 D-Cache Miss Rate (%) CPI 30 20 10 0 10 5 0 0 200 400 Instruction Interval (100M) 176.gcc 200 600 Fig. 3. L1 Data Cache and CPI behavior for gcc.200: this program exhibits complex behavior that is hard to capture with phase detection generate weights to apply to the intervals (and several SimPoints must be modeled for accurate results). By scaling the statistics by the corresponding weights, an accurate approximation of entire program behavior can be estimated quickly (within a small fraction of whole-application simulation time). 2.1 BBV Generation The BBV file format looks like: T:45:1024 :189:99343 T:11:78573 :15:1353 :56:1 T:18:45 :12:135353 :56:78 314:4324263 A T signifies the start of an interval, and is followed by a series of colon separated pairs; the first is a unique number specifying a basic block, and the second is the scaled frequency count. There are many methods for gathering information needed to create such BBV files. Requirements are that the tool count the number of committed instructions and track entries into every basic block. The SimPoint website only provides BBV generation tools using ATOM [14] and SimpleScalar [1] sim-alpha. These are useful for experiments involving the Alpha processor, but that architecture has declined in significance. There remains a need for tools to generate BBVs on a wider range of platforms. Our first attempt used DynInst [3], which supports many platforms, operating systems, and architectures. Unfortunately, the tool is not designed for generating BBVs, and memory overhead for instrumenting some of the benchmarks exceeds 4GB. Furthermore, the tool works with dynamically linked applications. We hope to use future versions, and work with the DynInst developers to generate BBVs without undue overheads. In contrast, Qemu [2] and Valgrind [9] already provide capabilities needed with acceptable overhead, and we modify these two DBI tools to generate BBVs. To validate our methods, we compare results to those from the Pin [7] tool. Figure 4 shows architectures supported for each tool; since all run on Intel platforms, we use them as a common reference.
Using Dynamic Binary Instrumentation 309 Pin Valgrind itanium arm x86 x86_64 ppc alpha sh4 m68k sparc mips cris hppa Qemu Fig. 4. Architectures supported by Pin, Qemu, and Valgrind: IA32 is the ideal platform for comparison, as it is supported by all of three tools 2.2 Pin Pin [7] is a dynamic binary instrumentation tool that runs on Intel architectures (including IA32, Intel 64, Itanium, and Xscale), and it supports Linux, Windows, and Macintosh OSX operating systems. We use the PinPoint [10] BBV generation tool bundled with version pin-2.0-10520-gcc.4.0.0-ia32-linux. Pin analysis routines are written in C++, and the instrumentation happens just-in-time, with the resulting instrumented code cached for performance. The core of Pin is proprietary, so internals must be treated as a black box. PinPoint analyses run from 1.5 (swim) to20(vortex) times slower than the binary run on native hardware. 2.3 Qemu Qemu [2] is a portable dynamic translator. It is commonly used to run a full operating system under hardware emulation, but it also has a Linux user-space emulator that runs stand-alone Linux binaries using system-call translation. Qemu supports the Alpha, SPARC, PowerPC, sh4, IA32, AMD64, MIPS, m68k, and ARM architectures. The user-mode translation we use is currently supported on Linux. Ongoing work will support more operating systems. Qemu uses gcc to compile code corresponding to each intermediate language micro-operation. At translation time, these pre-compiled micro-operations are chained together to create translated basic blocks that are cached. Qemu is not designed for DBI. Using it for our purposes requires intrusive changes to Qemu source. Our code is a patch applied on top of the Qemu 0.9.0 release. We add a unique identifier field to the internal TargetBlock basic block structure, which is set the first time a BB is translated. At translation time, we instrument every instruction to call our BBV tracking routine to update BBV counts and total instruction count. Once the interval size is reached, the BBV file is updated, and all counters are reset. Qemu runs from between 4 (art) to 40 (vortex) times slower than native execution. This makes it slower than Pin but faster than our Valgrind implementation.
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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avg normalized execution time 1.000
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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speed-up 8 6 4 2 0 FFT3D 256 64-A F
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Normalized Cycle Count 1.00 0.90 0.
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Integrated CPU Cache Power Manageme
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Variation-Aware Software Techniques
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Average leakage-power saving (%) Va
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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References Compiler Techniques for
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Code Arrangement of Embedded Java V
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Aggressive Function Inlining: Preve
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foo:(80 times) BB1: Call bar BB2: C
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400 Author Index Shajrawi, Yousef 3
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