Lecture Notes in Computer Science 4917

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f1(){ ...g();....} f2(){....q();....} Aggressive Function Inlining: Preventing Loop Blockings 387 m1(){ for(i=0;i
388 Y. Ben Asher et al. Table 1. Dynamic branch predictors on leading high-end embedded processors Processor BHT BTB Return Stack L1 I-cache AMCC 440GX 1024 16 – 32KB, 32B, 64 ways Broadcom BCM1250 1024 64 16 32KB, 32B, 4 ways Cavium Octeon 256 – 4 32KB, 32B, 4 ways IBM 750GX 512 64 – 32KB, 32B, 8 ways FreeScale MPC7447A 2048 2 – 32KB, 32B, 8 ways FreeScale MPC8560 512 512 – 32KB, 32B, 8 ways PMC-Sierra RM9000x2GL 256 – 4 32KB, 32B, 4 ways and 16-entry return address cache. On the other hand their L1 I-caches are in par with the aforementioned class of processors. The numbers demonstrate the importance of aggressive inlining techniques for embedded systems. 2 ILB Based Aggressive Function Inlining Inlining decisions are based on the Call Graph (CG) of the program. Each edge of the graph is assigned a weight: the frequency of each function call according to the profile information collected. The Average Heat ratio (AvgHeat) is the sum of all the frequencies of all the executed (dynamic) instructions (DI) gathered during the profiling stage, divided by the total number of static instructions (SI) in the program: �DI i freqi AvgHeat = SI Cold edges are defined as any edge in the extended CFG whose weight is lower than some threshold (e.g., 10%) of AvgHeat. The algorithm implementing the ILB method is: 1. Based on edge profile information, create the call graph CG for the given program and attach a weight to each edge. The weight is its execution frequency. 2. Traverse CG and remove all cold edges. Section 2.2 elaborates on this. 3. Remove cyclic paths from CG by finding the smallest weighted set of edges in CG using the algorithm of Eades et. al. [6] for solving the feedback edge set problem. Section 3 elaborates on this. 4. Let EG be the extended control flow graph containing the control flow graph of each function and direct edges for call and return instructions. For each function f in the call graph CG, which is a candidate for inlining: (a) For every two incoming edges e1 ande2 tof in CG, letcaller1 bethe caller basic block ending with e1 andletcaller2 be the caller basic block ending with e2 inEG. fallthru1 andfallthru2 arethebasicblocks following caller1 andcaller2 inEG respectively. (b) Traverse EG and search for directed paths from fallthru1 tocaller2 and from fallthru2 tocaller1. (c) If both paths exist, remove the e1 ande2 edgesfromCG.
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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Architecture Enhancements for the A
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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avg normalized execution time 1.000
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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180% 160% 140% 120% 100% 80% 60% 40
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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speed-up 8 6 4 2 0 FFT3D 256 64-A F
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Normalized Cycle Count 1.00 0.90 0.
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Integrated CPU Cache Power Manageme
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Variation-Aware Software Techniques
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Average leakage-power saving (%) Va
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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Turbo-ROB: A Low Cost Checkpoint/Re
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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266 P. Akl and A. Moshovos throttli
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268 P. Akl and A. Moshovos 80% 70%
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270 P. Akl and A. Moshovos 25% 20%
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272 P. Akl and A. Moshovos [4] Burg
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274 A. García et al. execution tim
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276 A. García et al. whenever LPA
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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Complementing Missing and Inaccurat
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6.1 Filling Edge Profile from Verte
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Using Dynamic Binary Instrumentatio
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L1 D-Cache Miss Rate (%) CPI 5 4 3
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CPI Error (%) 10 5 0 -5 -10 FP Resu
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CPI Error (%) 40 30 20 10 0 Using D
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Phase Complexity Surfaces: Characte
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( log10) phases of Number 4.0 3.5 3
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Page 406: 400 Author Index Shajrawi, Yousef 3
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Lecture Notes in Computer Science 4917

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