Tweaking Optimizing Windows.pdf - GEGeek

after a row activation can the same row be precharged for another cycle. If an exceedingly long tRAS is chosen, the row may be
unnecessarily delayed from precharging for another cycle. But if you set it for too short a period, there may not be enough time to
complete the read/write cycle. When that happens, data may be lost or corrupted.
For optimal performance, use the lowest value you can (5T in this case). But if you start getting memory errors or system
crashes, increase the value one clock cycle at a time until you get a stable system. Please note that because the bank cycle time
(tRC) = minimum row active time (tRAS) + row precharge time (tRP), you should take into account the values for tRC and tRP
before selecting the tRAS value.
DRAM data integrity mode
ECC, which stands for Error Checking and Correction, enables the memory controller to detect and correct single-bit soft memory
errors. The memory controller will also be able to detect double-bit errors although it will not be able to correct them. This provides
increased data integrity and system stability. However, this feature can only be enabled if you are using special ECC memory
modules. Now, this type of memory module is special (and more expensive!) as it comes extra memory chips and a wider path.
This is because the chipset needs to append a certain number of extra ECC bits (called ECC code) to each data word that's written
to the memory module. When the data word is read back, the memory controller will recalculate the ECC code of the read data word
and compare it to the original ECC code that was written to memory earlier. If the codes are identical, then the data is valid.
But if there's a single-bit error in the data word, the memory controller can identify the defective bit by analyzing the differences in
the two ECC codes. That bit can then be corrected by simply flipping it to the opposite state (from 0 to 1 and vice versa). Just for
general information, here's a list of ECC code length required for various data path widths using the current Hamming code
algorithm standard :-
Data Path Width ECC Code Length
8-bit 5 ECC bits
16-bit 6 ECC bits
32-bit 7 ECC bits
64-bit 8 ECC bits
128-bit 9 ECC bits
Because present day processors use 64-bit wide data paths, 72-bit (64-bit data + 8-bit ECC) ECC memory modules are required to
implement ECC. Please note that the maximum data transfer rate of the 72-bit ECC memory module is the same as the 64-bit
memory module. The extra 8-bits are only for the ECC code and do not carry any data. So, using 72-bit memory modules will not
give you any boost in performance. In fact, because the memory controller has to calculate the ECC code for every data word that
is read or written, there will be some performance degradation, roughly in the region of 3-5%. This is one of the reasons why ECC
memory modules aren't that popular. Throw in the fact that ECC memory modules are both expensive and hard to come by; and
you have the top three reasons why ECC memory modules will never be mainstream solutions.
But if data integrity is of utmost importance to you and you can't afford to have your system down due to errant cosmic rays or
radiation from the DRAM packaging, ECC memory is the only way to go. The loss of 3-5% in memory performance is really nothing,
compared to the peace of mind that ECC can give.
In any case, the matter of this BIOS feature is much easier to settle. If you are using standard 64-bit memory modules, you
must select the Non-ECC option. But if you already spent the extra dollar to get 72-bit ECC memory modules, you
should enable the ECC feature, no matter what people say about losing some memory performance. It doesn't make sense to
buy expensive ECC memory modules and then disable ECC! Remember, you are not really losing performance. You are just trading
it for greater stability and data integrity.
DRAM interleave time
This BIOS feature determines the amount of additional delay between successive bank accesses when the SDRAM Bank Interleave
feature has been enabled. Naturally, the shorter the delay, the faster the memory module can switch between banks and
consequently perform better. Therefore, it is recommended that you set the DRAM Interleave Time as low as possible for
better memory performance. In this case, it would be 0ms which introduces no additional delay between bank accesses. Increase
the DRAM Interleave Time to 0.5ms only if you experience stability problems.
DRAM prechrg to act cmd
Like SDRAM Trp Timing Value, this feature controls the memory bank's precharge time (tRP). This constitutes the time it takes for
the Precharge command to complete and the row to be available for activation. Hence the name DRAM PreChrg to Act CMD which is
short for DRAM Precharge Command to Activate Command. Now, tRP is important because it determines how soon a row can be
activated after a Precharge command has been issued. If an exceedingly long tRP is chosen, that may unnecessarily reduce
performance by preventing the row from being activated earlier. But if you set it for too short a period, the row may not be
sufficiently precharged and that may cause data loss or corruption when the memory controller attempts to read from that row.
For optimal performance, use the lowest value you can (2T in this case). But if you start getting memory errors or system
crashes, increase the value. Note that because the bank cycle time (tRC) = minimum row active time (tRAS) + row precharge
time (tRP), you should take into account the values for tRC and tRAS before selecting the tRP value.
DRAM read latch delay
This BIOS feature is similar to Delay DRAM Read Latch. It fine-tunes the DRAM timing parameters to adjust for different DRAM
loadings. The DRAM load changes with the number as well as the type of DIMMs installed. DRAM loading increases as the number of
DIMMs increases. It also increases if you use double-sided DIMMs instead of single-sided ones. In short, the more DRAM devices
you use, the greater the DRAM loading. As such, a single single-sided DIMM provides the lowest DRAM load possible.
With heavier DRAM loads, you may need to delay the moment when the memory controller latches onto the DRAM device during
reads. Otherwise, the memory controller may fail to latch properly onto the desired DRAM device and read from it. The longer the
delay, the poorer the read performance of your memory modules. However, the stability of your memory modules won't necessarily
improve if you enable this feature. Remember, the purpose of the feature is only to ensure that the memory controller will be able
to latch onto the DRAM device with all sorts of DRAM loadings.