Tweaking Optimizing Windows.pdf - GEGeek

Passive Release helps by allowing the write buffer to "passively write" to the PCI bus without CPU intervention and while the ISA
device is engaging the PCI bus. This essentially allows the CPU to indirectly write to the PCI bus even when the ISA device has
control over it. Without this feature, the PCI bus arbiter will only allow other (non-CPU) PCI masters to access the PCI bus. For best
performance, enable Passive Release. This will dramatically reduce the hogging effect of slow ISA devices on the PCI bus. However,
some ISA cards may not work well with Passive Release. In such cases, disable Passive Release or better yet, throw the card away
and get a PCI version!
If you don't use any ISA device, this feature should still be enabled because it will allow the write buffer to offload its data to
the PCI bus without waiting for the CPU to retry the transaction. This improves the CPU and PCI bus performance. Please note that
if you do not enable the CPU to PCI Write Buffer, this feature will have no effect.
PCI 2.1 compliance
This is the same thing as Delayed Transaction. The ISA bus is slower than the PCI bus. So, when the PCI bus wants to write to the
ISA bus, it has to wait until the ISA bus is ready. Because the ISA bus is many, many times slower than the PCI bus, the PCI bus is
normally stalled for a long time whenever a PCI cycle to the ISA bus is initiated. This prevents other devices from accessing the PCI
bus and can cause problems for time-critical applications that need constant access to the PCI bus.
To prevent the PCI bus from stalling every time it tries to write to the ISA bus, many chipsets now come with an embedded 32-bit
posted write buffer. This buffer is designed to store PCI-to-ISA writes and thus allows delayed transaction cycles to be generated.
When enabled, the PCI bus immediately writes up to two 16-bit or four 8-bit data to the write buffer. The PCI bus can then be freed
to perform other transactions. The buffer contents are independently written to the ISA bus when it's ready. Now, the data in the
write buffer won't reach the ISA bus any faster than usual. This is because they will only be written to the ISA bus when the next
available ISA cycle starts. But the difference here is that the entire operation can now occur without tying up the PCI bus.
This BIOS feature controls the operation of that embedded 32-bit posted write buffer. If enabled, up to four bytes of PCI-to-ISA
writes are buffered and the PCI bus is released after writing to the buffer. If PCI 2.1 Compliance is disabled, the PCI bus will bypass
the write buffer and write directly to the ISA bus.
It's highly recommended that you enable this feature for better PCI performance and to meet PCI 2.1 specifications. Disable it only
if your PCI cards cannot work properly with this feature enabled or if you are using an ISA card that is not PCI 2.1 compliant. Note
that PCI 2.1 Compliance is only important if you are actually using ISA devices. It is of no consequence at all if you are not using
any ISA devices or if your motherboard doesn't even come with ISA slots!
PCI chaining
PCI chaining feature is designed to speed up writes from the processor to the PCI bus by allowing write combining to occur at the
PCI interface. Essentially, when PCI chaining is enabled, up to four quadwords of CPU writes to contiguous PCI addresses will be
chained together and written to the PCI bus as a single PCI burst write. When this feature is disabled, each CPU write to the PCI bus
will be handled as separate non-burst writes. Needless to say, bursting four quadwords of CPU write in a single PCI write is much
faster than separate non-burst writes. It will also reduce the amount of time the CPU has to wait while writing to the PCI bus.
Therefore, it is recommended that you enable this feature for better CPU to PCI write performance.
PCI clock / CPU FSB clock
The PCI bus is specified to run at a maximum clock speed of 33MHz. The processor bus, on the other hand, has a much higher clock
speed. Most processors run on a 100MHz processor bus. Newer processors utilize an even faster 133MHz processor bus. Of course,
there are reports of overclockers reaching bus speeds in excess of 166MHz! The PCI bus speed is derived from the processor's bus
speed. It does this with the use of clock speed dividers.
This BIOS feature enables you to manually select the PCI bus / CPU bus clock divider. As this divider determines the speed that the
PCI bus will run at, the manipulation of this feature allows you some control over the PCI bus speed. As such, you can use it to
overclock the PCI bus. With that said, you should keep in mind that while some PCI cards can run at speeds beyond 41.5MHz, the
recommended safe limit for an overclocked PCI bus is 37.5MHz. This is the speed at which practically all new PCI cards can run at
without breaking a sweat.
Of course, running at a higher speed is definitely possible. But there's a risk of data corruption which is particularly worrisome with
the IDE controller which runs off the PCI bus. So, if you intend to overclock beyond 37.5MHz, test and make sure that your IDE
devices are running fine before you do any serious work!
Selecting the clock divider of 1/2 makes the PCI bus run at half the processor bus speed. If your processor bus is set to 100MHz,
the PCI bus speed will be 50MHz. As such, this clock divider is useful for processor bus speeds of 66MHz to 75MHz. Within that
range, the PCI bus will run from 33MHz to 37.5MHz.
Selecting the clock divider of 1/3 makes the PCI bus run at a third of the processor bus speed. If your processor bus is set to
100MHz, the PCI bus speed will be 33MHz. As such, this clock divider is useful for processor bus speeds of 100MHz to 112.5MHz.
Within that range, the PCI bus will run from 33MHz to 37.5MHz.
Selecting the clock divider of 1/4 makes the PCI bus run at a quarter of the processor bus speed. If your processor bus is set to
100MHz, the PCI bus speed will be 25MHz. As such, this clock divider is useful for processor bus speeds of 133MHz to 150MHz.
Within that range, the PCI bus will run from 33MHz to 37.5MHz.
You will probably be wondering about the gaps in the covered processor bus speeds above. Well, only processor bus speeds that will
produce PCI clock speeds that are within the range of optimal PCI clock speeds (33MHz to 37.5MHz) are shown above. The other
processor bus speeds will either produce a slow PCI bus or an excessively overclocked one. Therefore, for optimal PCI bus
performance, try to strike for one of the processor bus speed-divider combinations shown above.
Please note that motherboards that claim 200-266MHz processor bus speeds are actually only running at 100-133MHz. The 200-
266MHz claim is based on the fact that in these motherboards, data is transferred on both edges of the clock signal, thereby