Tweaking Optimizing Windows.pdf - GEGeek

doubling the bandwidth of the processor bus. Therefore, as far as this feature is concerned, such motherboards are only running at
100-133MHz.
PCI delay transaction
This is the same thing as Delayed Transaction. The ISA bus is slower than the PCI bus. So, when the PCI bus wants to write to the
ISA bus, it has to wait until the ISA bus is ready. Because the ISA bus is many, many times slower than the PCI bus, the PCI bus is
normally stalled for a long time whenever a PCI cycle to the ISA bus is initiated. This prevents other devices from accessing the PCI
bus and can cause problems for time-critical applications that need constant access to the PCI bus.
To prevent the PCI bus from stalling every time it tries to write to the ISA bus, many chipsets now come with an embedded 32-bit
posted write buffer. This buffer is designed to store PCI-to-ISA writes and thus allows delayed transaction cycles to be generated.
When enabled, the PCI bus immediately writes up to two 16-bit or four 8-bit data to the write buffer. The PCI bus can then be freed
to perform other transactions. The buffer contents are independently written to the ISA bus when it's ready.
Now, the data in the write buffer won't reach the ISA bus any faster than usual. This is because they will only be written to the ISA
bus when the next available ISA cycle starts. But the difference here is that the entire operation can now occur without tying up the
PCI bus. This BIOS feature controls the operation of that embedded 32-bit posted write buffer. If enabled, up to four bytes of PCIto-ISA
writes are buffered and the PCI bus is released after writing to the buffer. If PCI Delay Transaction is disabled, the PCI bus
will bypass the write buffer and write directly to the ISA bus.
It's highly recommended that you enable this feature for better PCI performance and to meet PCI 2.1 specifications. Disable it only
if your PCI cards cannot work properly with this feature enabled or if you are using an ISA card that is not PCI 2.1 compliant. Note
that PCI Delay Transaction is only important if you are actually using ISA devices. It is of no consequence at all if you are not using
any ISA devices or if your motherboard doesn't even come with ISA slots!
PCI dynamic bursting
This is similar to the Byte Merge feature. If you have already read about the CPU to PCI Write Buffer feature, you should know that
the chipset has an integrated write buffer which allows the CPU to immediately write up to four words of PCI writes to it, thus
freeing it quickly and allowing it to work on other tasks. However, the CPU doesn't always write 32-bit data to the PCI bus. 8-bit
and 16-bit writes can also take place. But while the CPU may write 8-bits of data to the PCI bus, it is considered as a single PCI
transaction, equivalent to a 16-bit or 32-bit write. This reduces the effective PCI bandwidth, especially if there are many 8-bit or 16-
bit CPU-to-PCI writes.
To solve this problem, the write buffer can be programmed to accumulate and merge 8-bit and 16-bit writes into 32-bit writes. The
buffer then writes the merged data to the PCI bus. As you can see, merging the smaller 8-bit or 16-bit writes into a few large 32-bit
writes reduces the number of PCI transactions required. This increases the efficiency of the PCI bus and improves its bandwidth.
This feature controls the dynamic bursting capability of the PCI write buffer. If it is enabled, every write transaction will go straight
to the write buffer. They are accumulated until enough data is available to be written to the PCI bus in a single burst. This improves
the PCI bus' performance so it's recommended that you enable this feature.
If you disable PCI dynamic bursting, all writes will still go to the PCI write buffer (if CPU to PCI Write Buffer has been enabled). But
the buffer won't accumulate and merge the data. The data is written to the PCI bus as soon as it is free. As such, there may be a
loss of PCI bus efficiency, particularly when 8-bit or 16-bit data is written to the bus.
Note that like Byte Merge, this feature may not be compatible with certain PCI network interface cards. For more details,
please check out the Byte Merge feature.
PCI IRQ activated by
This BIOS feature allows you to set the method by which the IRQs for your PCI devices are activated or triggered. ISA and old PCI
devices are edge-triggered (using a single voltage level) while newer PCI and AGP devices are level-triggered (using multiple
voltage levels). This is important mainly because PCI devices must be level-triggered to share IRQs. The multiple voltage levels
supported by level-triggered cards are used to activate the proper device among multiple devices sharing the same IRQ. Edgetriggered
devices only support a single voltage level which can only be used to activate or deactivate their IRQs. Therefore, IRQs
allocated to edge-triggered devices cannot be shared with other devices.
When PCI devices were initially introduced, they were almost always edge-triggered and therefore didn't support IRQ sharing. That's
why the default and recommended setting for older PCI devices was invariably Edge. Unfortunately, that misled people into thinking
that it would be the same for newer PCI devices.
Current PCI devices are all level-triggered and so support IRQ sharing. This is critical in allowing the use of the numerous PCI
devices in present day computers. Without IRQ sharing, IRQ conflicts would have posed serious configuration problems. Of course,
the introduction of the Advanced Programmable Interrupt Controller or APIC solves this problem completely by providing anywhere
from 24 to 512 IRQ lines! But until all motherboards come with APIC, IRQ sharing will continue to play an important role in allowing
multiple PCI devices to work in harmony.
Because every PCI device currently in the market is level-triggered, it makes sense to set this BIOS feature to Level so that your
PCI devices can share IRQs. However, if you are still using old edge-triggered devices, select Edge to force the chipset to
allow only edge-triggering of PCI devices. This may cause configuration problems if there are IRQ conflicts but it will prevent
system crashes or lockups that can occur if the chipset erroneously attempts to level-trigger an edge-triggered PCI device.
PCI latency timer
This feature controls how long a PCI device can hold the PCI bus before another takes over. The larger the value, the longer the PCI
device can retain control of the bus. As each access to the bus comes with an initial delay before any transaction can be made, a
short PCI latency time will actually reduce the effective PCI bandwidth while longer latencies improve it. On the other hand, while
increasing the PCI latency time lets each PCI device access the bus longer, the response time of all PCI devices suffers in return. In
other words, a long PCI latency will allow active PCI device to use the PCI bus longer albeit at the expense of other PCI devices
queuing up to use the bus. All PCI devices will therefore have to wait longer before gaining access to the bus.