Tweaking Optimizing Windows.pdf - GEGeek

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This feature determines how long the memory controller should wait before sending the read data to the data requester (i.e. processor, graphics card, etc..). By default, a wait state is added before the data is sent to the requester. Therefore, read performance is reduced because the memory controller has to wait one cycle before sending any data. In addition, to prevent overlapping of a read and a write request when the Read Wait State is set to 1 Cycle, an additional delay cycle is inserted between every read cycle that is followed immediately by a write cycle. This is similar to disabling the Fast R-W Turn Around feature. This effectively reduces the memory write performance. Therefore, it is recommended that you set the Read Wait State to 0 Cycle for better memory read and write performance. Note that this may cause system instabilities in certain situations. When that happens, just reset the value to 1 Cycle. Read around write This BIOS feature allows the processor to execute read commands out of order, as if they are independent from the write commands. It does this by using a Read-Around-Write buffer. Writes are accumulated in this buffer and then written to memory as a burst transfer. This reduces the number of writes to memory and boosts the memory subsystem's read performance. In addition, the Read-Around-Write buffer serves as a cache of the most up-to-date data that hasn't been written to memory yet. So, if a read command points to a memory address whose latest write (content) is still in the Read-Around-Write buffer (waiting to be copied into memory), the read command will be satisfied by the cache contents instead. In short, if the Read-Around-Write buffer has the data, the processor can directly read from it, without waiting to access the memory (which will take more time). This further improves the memory's read performance. Therefore, it is highly recommended that you enable this feature for better memory read performance. Refresh interval Memory cells normally need to be refreshed every 64 msec. However, simultaneously refreshing all the rows in a typical memory chip will cause a big surge in power requirements. In addition, a simultaneous refresh causes all data requests to stall, which greatly impacts performance. To avoid both problems, refreshes are normally staggered according to the number of rows. Since a typical memory chip contains 4096 rows, the memory controller usually refreshes a different row every 15.6 µsec (64,000 µsec / 4096 rows = 15.6 µsec). This reduces the amount of current used during each refresh and it allows data to be accessed from the other rows. Usually, DIMMs that use 128Mbit or smaller memory chips have 4096 rows while memory chips with higher capacity (256Mbit and above) will have 8192 rows. For memory chips that come with 8192 rows, the refresh interval will need to be halved to 7.8 µsec because there are now twice as many rows to serviced within the stipulated 64 msec for the entire chip. Therefore, the typical refresh interval for 128Mbit (not MB!) or smaller memory chips would be 15.6 µsec while those for 256Mbit or larger memory chips would be 7.8 µsec. Please note that if you are using a mix of 128Mbit or smaller DIMMs with 256Mbit or larger DIMMs, the fail-safe Refresh Interval would be 7.8 µsec, not 15.6 µsec. Although JEDEC standards call for a 64 msec refresh cycle, memory chips these days can actually hold data for longer than that. So, using a longer refresh cycle is quite possible. With a longer refresh cycle, the memory chips are refreshed less often, reducing both the amount of bandwidth wasted on refreshes and the amount of power consumed (which is great for laptops and other portable devices). For better performance, you should consider increasing the Refresh Interval from the default values (15.6 µsec for 128Mbit or smaller memory chips and 7.8 µsec for 256Mbit or larger memory chips) up to 128 µsec. Please note that if you increase the Refresh Interval too much, the memory cells may lose their contents. Therefore, you should start with small increases in the Refresh Interval and test your system after each hike before increasing it further. If you face stability problems upon increasing the Refresh Interval, reduce the Refresh Interval step by step until the system is stable. Refresh mode select Memory cells normally need to be refreshed every 64 msec. However, simultaneously refreshing all the rows in a typical memory chip will cause a big surge in power requirements. In addition, a simultaneous refresh causes all data requests to stall, which greatly impacts performance. To avoid both problems, refreshes are normally staggered according to the number of rows. Since a typical memory chip contains 4096 rows, the memory controller usually refreshes a different row every 15.6 µsec (64,000 µsec / 4096 rows = 15.6 µsec). This reduces the amount of current used during each refresh and it allows data to be accessed from the other rows. Usually, DIMMs that use 128Mbit or smaller memory chips have 4096 rows while memory chips with higher capacity (256Mbit and above) will have 8192 rows. For memory chips that come with 8192 rows, the refresh interval will need to be halved to 7.8 µsec because there are now twice as many rows to serviced within the stipulated 64 msec for the entire chip. Therefore, the typical refresh interval for 128Mbit (not MB!) or smaller memory chips would be 15.6 µsec while those for 256Mbit or larger memory chips would be 7.8 µsec. Please note that if you are using a mix of 128Mbit or smaller DIMMs with 256Mbit or larger DIMMs, the fail-safe refresh interval would be 7.8 µsec, not 15.6 µsec. Although JEDEC standards call for a 64 msec refresh cycle, memory chips these days can actually hold data for longer than that. So, using a longer refresh cycle is quite possible. With a longer refresh cycle, the memory chips are refreshed less often, reducing both the amount of bandwidth wasted on refreshes and the amount of power consumed (which is great for laptops and other portable devices). For better performance, you should consider increasing the Refresh Mode Select from the default values (15.6 µsec for 128Mbit or smaller memory chips and 7.8 µsec for 256Mbit or larger memory chips) up to 128 µsec. Please note that if you increase the Refresh Mode Select too much, the memory cells may lose their contents. Therefore, you should start with small increases in the Refresh Mode Select and test your system after each hike before increasing it further. If you face stability problems upon increasing the Refresh Mode Select, reduce it step by step until the system is stable. SDRam Bank Interleave This feature enables you to set the interleave mode of the SDRAM interface. Interleaving allows banks of SDRAM to alternate their refresh and access cycles. One bank will undergo its refresh cycle while another is being accessed. This improves performance of the SDRAM by masking the refresh time of each bank. A closer examination of interleaving will reveal that since the refresh cycles of all the SDRAM banks are staggered, this produces a kind of pipelining effect. If there are 4 banks in the system, the CPU can ideally send one data request to each of the SDRAM banks in consecutive clock cycles. This means in the first clock cycle, the CPU will send an address to Bank 0 and then send the next address to Bank 1 in the
second clock cycle before sending the third and fourth addresses to Banks 2 and 3 in the third and fourth clock cycles respectively. The sequence would be something like this :- As a result, the data from all four requests will arrive consecutively from the SDRAM without any delay in between. But if interleaving was not enabled. With interleaving, the first bank starts transferring data to the CPU in the same cycle that the second bank receives an address from the CPU. Without interleaving, the CPU would send the address to the SDRAM, receive the data requested and then wait for the SDRAM to refresh before initiating the second data transaction. This wastes a lot of clock cycles. That's why the memory bandwidth increases when interleaving is enabled. However, bank interleaving only works if the addresses requested consecutively are not in the same bank. If they are, then the data transactions behave as if the banks were not interleaved. The CPU will have to wait until the first data transaction clears and that SDRAM bank refreshes before it can send another address to that bank. Each SDRAM DIMM consists of either 2 banks or 4 banks of memory. 2-banked SDRAM DIMMs use 16Mbit SDRAM chips and are usually 32MB or less in size. 4-banked SDRAM DIMMs, on the other hand, usually use 64Mbit SDRAM chips though the SDRAM density may be up to 256Mbit per chip. All SDRAM DIMMs of at least 64MB in size or greater are 4-banked in nature. If you are using a single 2-banked SDRAM DIMM, set this feature to 2-Bank. But if you are using two 2-banked SDRAM DIMMs, you can use the 4-Bank option as well. With 4-banked SDRAM DIMMs, you can use either interleave options. Naturally, 4-bank interleave is better than 2-bank interleave so if possible, set it to 4-Bank. Use the 2-Bank option only if you are using a single 2-banked SDRAM DIMM. Please note, however, that Award (now part of Phoenix Technologies) recommends that SDRAM bank interleaving be disabled if 16Mbit SDRAM DIMMs are used. This is because early 16Mbit SDRAM DIMMs used to have stability problems with bank interleaving. All current SDRAM modules can use bank interleaving without stability problems though. SDRam cas latency time This BIOS feature controls the time delay (in clock cycles) that passes before the SDRAM module starts to carry out a read command after receiving it. It also determines the number of clock cycles required for the completion of the first part of a burst transfer. In other words, the lower the latency, the faster memory reads can occur. Please note that some SDRAM modules may not be able to handle the lower latency and may lose data. Therefore, set the SDRAM CAS Latency Time to 2 for better memory read performance but increase it to 3 (2.5 in DDR memory) if your system becomes unstable. Interestingly, increasing the CAS latency time does have an advantage in that it will often allow the SDRAM module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM module(s), try increasing the CAS latency time. SDRam cycle length This feature is same as the SDRAM CAS Latency Time feature. This BIOS feature controls the time delay (in clock cycles) that passes before the SDRAM module starts to carry out a read command after receiving it. It also determines the number of clock cycles required for the completion of the first part of a burst transfer. In other words, the lower the latency, the faster memory reads can occur. Please note that some SDRAM modules may not be able to handle the lower latency and may lose data. Therefore, set the SDRAM Cycle Length to 2 for better memory read performance but increase it to 3 (2.5 in DDR memory) if your system becomes unstable. Interestingly, increasing the cycle length does have an advantage in that it will often allow the SDRAM module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM module(s), try increasing the cycle length. SDRam cycle time tras/trc This feature determines the minimum number of clock cycles required for the Tras and the Trc of the SDRAM. Tras refers to the SDRAM's Row Active Time, which is the length of time the row will remain open for data transfers. It is also known as Minimum RAS Pulse Width. Trc, on the other hand, refers to the SDRAM's Row Cycle Time, which determines the length of time for the entire rowopen to row-refresh cycle to complete. The default setting is 6/8 which is more stable and slower than 5/6. The 5/6 setting cycles the SDRAM faster but may not leave the row open long enough for data transactions to complete. When this happens, the contents of the memory cells may be corrupted. This is especially true at SDRAM clockspeeds above 100MHz. Therefore, you should try 5/6 for better SDRAM performance and only increase it to 6/8 if your system becomes unstable. You can also use the slower 6/8 setting if you are trying to overclock your SDRAM modules as it may allow the modules to run at a higher clockspeed. SDRam idle limit This feature sets the number of idle cycles a SDRAM bank has to wait before recharging. It allows you to improve the efficiency of the SDRAM read and write cycles by adjusting the amount of time that the bank is allowed to remain idle before it is recharged. Increasing the SDRAM Idle Limit to more than the default of 8 cycles allows the SDRAM bank to delay recharging longer during times of no activity so that if a read or write command comes along, it can be instantly satisfied. However, this is limited by the refresh cycle already set by the BIOS. That means the SDRAM bank will refresh when it needs to be recharged whether the number of idle cycles have reached the SDRAM Idle Limit or not. So, the SDRAM Idle Limit setting can only be used to force the refreshing of the SDRAM bank before the set refresh cycle but not to actually delay the refresh cycle. Reducing the number of cycles from the default of 8 cycles to 0 cycles forces the SDRAM bank to initiate a refresh cycle once no valid requests are sent to the memory controller. In short, the SDRAM bank is refreshed as soon as it is idle. Theoretically, this may increase the efficiency of the SDRAM as the effects of refreshing the banks are masked because they are done during idle cycles. However, if there are any data requests after the bank starts its refresh cycle, they will have to wait until the bank is completely refreshed and activated before they can be satisfied. Because refreshes do not occur that often (usually only about once every 64 msec), the impact of refreshes on SDRAM performance is really quite minimal and the benefits of masking the SDRAM's refreshes during idle cycles will not be noticeable. In fact, there's a high risk that data requests will get stalled more often, especially with the idle limit of 0 cycle. As such, you are more likely to see reduced performance with the 0 cycles setting, especially since even a single idle cycle will cause the bank to go into a bandwidthexpensive refresh cycle. On the plus side, the contents of the memory cells will be refreshed more often and there will be little chance of losing data due to insufficiently refreshed memory cells. For best performance, this feature should be disabled so that
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Mr.X.'s TWEAKING AND OPTIMIZING WIN
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If you have Windows 95/NT you can e
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Page 115 and 116: SDRam RAS precharge time This featu
Page 117 and 118: The shorter the delay, the earlier
Page 119 and 120: CPU level 1 cache The modern proces
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Page 129 and 130: This feature allows you to manually
Page 131 and 132: doubling the bandwidth of the proce
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Page 137 and 138: You will notice that the interrupts
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Page 147 and 148: 5.0x 500Mhz 560Mhz 620Mhz 665Mhz 5.
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