Tweaking Optimizing Windows.pdf - GEGeek

Normally, the PCI Latency Timer is set to 32 cycles. For better PCI performance, a larger value should be used. Try increasing it to
64 cycles or even 128 cycles. The optimal value for every system is different. So, benchmark your PCI cards' performance after
each change to determine the optimal PCI latency time for your system.
Note that a longer PCI latency isn't necessarily better. Too long a latency can reduce performance as too much time may be
allocated to each PCI device to the disadvantage of the other devices on the bus. This is especially true with systems that have
many PCI devices. Also, some time-critical PCI devices may not agree with a long latency so if you start facing problems with
one or more of your PCI devices, reduce the latency.
PCI master 0 WS read
This feature determines whether the chipset inserts a delay before any reads from the PCI bus. If this is enabled, then read
requests to the PCI bus are executed immediately (with zero wait states), if the PCI bus is ready to send data. But if it is disabled,
then every read request to the PCI bus is delayed by one wait state. Normally, it is recommended that you enable this feature
for faster PCI performance. However, disabling it may be useful when attempting to stabilize an overclocked PCI bus.
The delay will generally improve the overclockability and stability of the PCI bus.
PCI master 0 WS write
This feature determines whether the chipset inserts a delay before any writes to the PCI bus. If this is enabled, then writes to the
PCI bus are executed immediately (with zero wait states), if the PCI bus is ready to receive data. But if it is disabled, then every
write transaction to the PCI bus is delayed by one wait state. Normally, it is recommended that you enable this feature for
faster PCI performance. However, disabling it may be useful when attempting to stabilize an overclocked PCI bus. The
delay will generally improve the overclockability and stability of the PCI bus.
PCI master read caching
Just like Video RAM Cacheable, this feature may actually hinder performance although it was designed to improve it. How is that so?
If this feature is enabled, the processor's L2 cache will be used to cache PCI bus master reads. This was designed to boost the
performance of PCI bus masters. However, this reduces the processor's performance since it uses up some of the precious L2
cache.
That's why ASUS recommends that only those using AMD Athlons should enable this feature. Duron users should disable this feature
because its small L2 cache will not be able to cache the PCI reads without a massive hit to memory bandwidth. However, it is
questionable that even Athlon systems will really benefit from this feature. For one thing, the Athlon doesn't have so much L2 cache
that using it to boost PCI bus masters' performance won't detrimentally affect its performance. And just like the Video RAM
Cacheable feature, it involves two-way use of the processor bus (the EV6 bus in this case), which reduces its efficiency and the
processor's performance as well.
So, does the boost in PCI bus master performance justify the loss in processor and memory performance? Although the final word is
still in the air, I recommend disabling this feature. IMHO, the use of precious L2 cache to cache PCI bus masters is just not
worth the potential benefit in PCI bus performance.
PCI pipelining
This BIOS feature determines if PCI transactions to the memory subsystem will be pipelined. If enabled, the memory controller
allows PCI transactions to be pipelined. This masks the latency of the PCI bus which greatly improves the efficiency of the bus.
However, this is only true for multiple transactions in the same direction. Pipelining won't help with PCI devices that switch between
reads and writes often. This feature is different from a burst transfer in which multiple data are transferred consecutively with only
a single command. In PCI pipelining, different transactions are preprocessed in the pipeline without waiting for the current
transaction to finish. Normally, outstanding transactions have to wait for the current one to complete before they are initiated.
Please note that because the transactions are pipelined and flagged as performed (even though they have not actually been
completed), data coherency problems may occur. This is because other devices may be writing to the same block of memory as the
PCI device. This may cause valid data to be overwritten by outdated or expired data, causing problems like data corruption or hard
system locks.
If the PCI pipeline is disabled, the memory controller is forced to check for outstanding transactions from other devices to the same
block address that each PCI transaction is targeting. If there's a match, then the PCI transaction is stalled until the other transaction
has completed. This essentially forces the memory controller to hold the PCI bus until the PCI transaction is cleared to occur. It also
prevents PCI transactions from being pipelined. Both factors greatly reduce performance.
Therefore, for better performance, the PCI pipeline should be enabled. This allows the latency of the bus to be masked for
consecutive transactions. However, if your system constantly locks up for no apparent reason, try disabling this feature.
Disabling PCI Pipelining reduces performance but ensures that data coherency is strictly maintained for maximum
reliability.
PCI prefetch
This feature controls the system controller's PCI prefetch capability. When enabled, the system controller will prefetch eight
quadwords (or one cache line) of data from the SDRAM when a PCI device reads from the main memory. This is done on the
assumption that PCI device will request the next cache line of data. This allows subsequent contiguous memory accesses by the
same PCI device to occur with minimal delay. So, it is recommended that you enable this feature for better PCI read performance
PCI target latency
This feature determines if the system controller conforms to the PCI maximum target latency rule. According to the PCI maximum
target latency rule, the PCI device must service a read request within 32 PCI clock cycles for the initial read and 8 PCI clock cycles
for each subsequent read. Note that this only applies to the PCI bus. It does not apply to the AGP bus. When this feature is
disabled, the PCI bus master will not be disconnected when it cannot service a read request within the stipulated 32 PCI clock cycles
for the initial read and 8 PCI clock cycles for subsequent reads.