Tweaking Optimizing Windows.pdf - GEGeek

This feature allows you to manually select the I/O address and IRQ for the first serial port. It is recommended that you leave it as
Auto so that the BIOS can select the best settings for it. But if you need a particular I/O port or IRQ that's been taken up by this
serial port, you can manually select an alternative I/O port or IRQ for it. You can also disable this serial port if you do not need
to use it. Doing so frees up the I/O port and IRQ used by this serial port. Those resources can then be reallocated for other devices
to use.
Onboard serial port 2
This feature allows you to manually select the I/O address and IRQ for the second serial port. It is recommended that you leave it
as Auto so that the BIOS can select the best settings for it. But if you need a particular I/O port or IRQ that's been taken up by this
serial port, you can manually select an alternative I/O port or IRQ for it. You can also disable this serial port if you do not need
to use it. Doing so frees up the I/O port and IRQ used by this serial port. Those resources can then be reallocated for other devices
to use.
Onboard USB controller
This BIOS feature is somewhat similar to Assign IRQ For USB. But instead of controlling the assignment of an IRQ to the
motherboard's onboard USB controller, this feature directly controls the function of the onboard USB controller. Enable this feature if
you want to attach your USB devices to the onboard USB controller. If you disable this feature, the USB controller will be disabled
and you won't be able to connect any USB devices to it. But if you don't use any USB devices, this frees up an IRQ for other
devices to use. This is particularly useful when you have many devices that can't share IRQs. Disabling this feature may not be
necessary with APIC-capable motherboards because they come with more IRQs.
P2C/C2P concurrency
P2C/C2P Concurrency enables the PCI-to-CPU and CPU-to-PCI traffic to occur concurrently (simultaneously). This prevents the CPU
from being "locked up" during PCI transfers. It also allows PCI traffic to the processor to occur without delay even when the
processor is writing to the PCI bus. This may prevent performance issues with certain PCI cards. Therefore, it is recommended that
you enable this feature for better performance.
Parallel port mode
This function is usually found under the Onboard Parallel Port feature. It's linked to the parallel port so if you disable the parallel
port, this function will not appear or will appear greyed out. There are four options. By default, the parallel port is usually set to the
Normal (SPP) mode. SPP stands for Standard Parallel Port and it is the original transfer protocol for the parallel port. Therefore, it
will work with all parallel port devices.
Originally a unidirectional port, the SPP was eventually adapted to work bidirectionally. So, contrary to popular opinion, the SPP
mode is capable of bidirectional transfers. However, it can only receive 4-bits of data in this bidirectional mode. Its output,
fortunately, remains at 8-bits. This gives the parallel port in SPP mode an output rate of 150KB/s and an input rate of 50KB/s. The
ECP (Extended Capabilities Port) transfer mode was introduced by Microsoft and Hewlett-Packard to provide fast, bidirectional
communication between the computer and high-performance printers and scanners. It uses the DMA protocol to achieve data
transfer rates of up to 2MB/s and provides symmetric bidirectional communication.
On the other hand, EPP (Enhanced Parallel Port), now known as IEEE 1284, uses existing parallel port signals to provide asymmetric
bidirectional communication. It was also designed for high-speed communications, offering transfer rates of up to 2MB/s. As you
can see, SPP is a very slow transfer mode. It should only be selected when faster transfer modes cannot be used (i.e. with old
printers or scanners). With modern parallel port devices, the ECP and EPP modes are the transfer modes of choice.
Generally, because of its FIFOs and the DMA channel it uses, ECP is good at large data transfers. Therefore, it is the transfer mode
that works best with scanners and printers. EPP is better with devices that switch between reads and writes frequently (like ZIP
drives and hard disks). This tip was obtained from Jan Axelson's Parallel Port FAQ so check it out if you require more information on
parallel ports.
However, before you set the transfer mode, please check your parallel port device's documentation. The manufacturer of
your parallel port peripheral may have designated a preferred parallel port mode for the device in question. In that case, it is best to
follow their recommendation. If the device documentation did not state any preferred transfer mode and you still do not know what
mode to select, you can select the ECP+EPP mode. If you select this mode, the BIOS will automatically determine the transfer mode
to use for your device.
However, this should be considered as a last resort as you may be needlessly tying up a DMA for nothing if your device does not
use ECP at all. Or the BIOS may not select the best parallel port mode for the device. If possible, set the parallel port to the
transfer mode that best suits your parallel port device.
Passive release
If you have already read about the CPU to PCI Write Buffer feature, you should know that the chipset has an integrated write buffer
that allows the CPU to immediately write up to four words of PCI writes to it, thus freeing it quickly and allowing it to work on other
tasks. This BIOS feature controls the passive release function of the CPU to PCI Write Buffer. So, if the write buffer is disabled, this
function will not have any effect. However, the reverse isn't true. The CPU to PCI Write Buffer feature will still work even if Passive
Release is disabled.
What Passive Release does is allow the write buffer to independently write the data to the PCI bus at the first available opportunity.
It can do so even when the processor is busy doing something else. Without Passive Release, the write buffer waits till the CPU
reasserts the write request before it writes to the PCI bus. This still saves time (and improves performance) because the CPU
doesn't actually need to resend the data. The write buffer is ready to offload the data the moment the PCI bus arbiter releases
control of the bus to the CPU. However, because the write buffer has to wait for the CPU to retry the transaction, this reduces its
effectiveness.
This is a particularly big problem when an ISA device engages the ISA bus. Because the ISA bus is very slow, this ties up the PCI
bus and prevents the CPU from accessing it for a very long time. If the CPU-to-PCI write buffer had been enabled, the CPU
immediately writes to the buffer. This frees the CPU to engage in other tasks but the write buffer cannot write to the PCI bus until
both the CPU is free to retry the write and the PCI bus is free to receive.