Tweaking Optimizing Windows.pdf - GEGeek

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mode switching is required, then it doesn't matter at all if the switching was done by the slow keyboard controller or the faster 0x92 port. With all is said and done, however, the recommended setting for this BIOS feature is still Fast even with operating systems that don't do much mode switching. Except for very rare instances in which using the 0x92 port to control Gate A20 causes spontaneous reboots, there's no reason why you should keep using the slow keyboard controller to turn A20 or or off. In order queue depth For greater performance at high clock speeds, motherboard chipset designs now feature a pipelined processor bus. The multiple stages in this pipeline can further be used to queue up multiple commands to the processor. This command queuing greatly improves performance because it effectively masks the latency of the processor bus. In optimal situations, the amount of latency between each succeeding command can be reduced to only a single clock cycle! This BIOS feature controls the use of the processor bus' command queue. Normally, there are only two options available. Depending on the motherboard chipset, the options could be (1 and 4), (1 and 8) or (1 and 12). This is because this BIOS feature actually only allows you to disable or enable the command queuing capability of the processor bus pipeline. It does not allow you to control the number of commands that can be queued. This is because the number of commands that can be queued depends entirely on the number of stages in the pipeline. As such, you can expect to see this feature associated with options like Enabled and Disabled in some motherboards. The first queue depth option is always 1, which prevents the processor bus pipeline from queuing any outstanding commands. If selected, each command will only be issued after the processor has finished with the previous one. Therefore, every command will incur the maximum amount of latency. This varies from 4 clock cycles for a 4-stage pipeline to 12 clock cycles for pipelines with 12 stages. As you can see, this reduces performance as the processor has to wait for each command to filter down the pipeline. The severity of the effect depends greatly on the depth of the pipeline. The deeper the pipeline, the greater the effect. If the second queue depth option is 4, this means that the processor bus pipeline has 4 stages in it. Selecting this option allows the queuing of up to 4 commands in the pipeline. Each command can then be processed successively with a latency of only 1 clock cycle. If the second queue depth option is 8, this means that the processor bus pipeline has 8 stages in it. Selecting this option allows the queuing of up to 8 commands in the pipeline. Each command can then be processed successively with a latency of only 1 clock cycle. If the second queue depth option is 12, this means that the processor bus pipeline has 12 stages in it. Selecting this option allows the queuing of up to 12 commands in the pipeline. Each command can then be processed successively with a latency of only 1 clock cycle. Please note that the latency of only 1 clock cycle is only possible if the pipeline is completely filled up. If the pipeline is only partially filled up, then the latency affecting one or more of the commands will be more than 1 clock cycle. Still, the average latency for each command will be much lower than it would be with command queuing disabled. In most cases, it is highly recommended that you enable command queuing by selecting the options of 4 / 8 / 12 or in some cases, Enabled. This allows the processor bus pipeline to mask its latency by queuing outstanding commands. You can expect a significant boost in performance with this feature enabled. Interestingly, this feature can also be used as an aid in overclocking the processor. Although the queuing of commands brings with it a big boost in performance, it may also make the processor unstable at overclocked speeds. To overclock beyond what's normally possible, you can try disabling command queuing. This may reduce performance but it will make the processor more stable and may allow it to be further overclocked. But please note that the performance deficit associated with deeper pipelines (8 or 12 stages) may not be worth the increase in processor overclockability. This is because the deep processor bus pipelines have very long latencies. If they are not masked by command queuing, the processor may be stalled so badly that you may end up with poorer performance even if you are able to further overclock the processor. So, it is recommended that you enable command queuing for deep pipelines, even if it means reduced overclockability. Level 2 cache latency Whenever the processor's Level 2 cache receives a read/write command, a certain period of time passes before the cache can actually process the command. This delay is called latency and the shorter the latency, the faster the Level 2 cache can service data reads/writes. This BIOS feature enables you to change the latency of the processor's Level 2 cache. By default, this feature is set to Auto which means that the processor's Level 2 cache will be left to its default latency setting. This is the safest option. You can also manually select the latency of the cache. For this purpose, this BIOS feature provides options ranging from 1 clock cycle to 15 clock cycles. Please note that setting too low a latency can cause the Level 2 cache to lose data integrity or fail altogether. This will manifest as a system crash or an inability to boot-up at all. Therefore, it is recommended that you start with a high latency and work your way down until you start to encounter stability issues. This allows you to figure out what's the lowest latency your processor's Level 2 cache can support. Select that latency for optimal performance without stability issues. Please note that this is a processor-dependent feature. Not all processors support BIOS manipulation of the Level 2 cache latency. If the processor does not support the manipulation of its Level 2 cache latency, then this BIOS feature will not have any effect, irrespective of what you select. MPS control version for OS This feature is only applicable to multiprocessor motherboards as it specifies the version of the Multi-Processor Specification (MPS) that the motherboard will use. The MPS is a specification by which PC manufacturers design and build Intel architecture systems with two or more processors.
MPS 1.1 was the original specification. MPS version 1.4 adds extended configuration tables for improved support of multiple PCI bus configurations and greater expandability in the future. In addition, MPS 1.4 introduces support for a secondary PCI bus without requiring a PCI bridge. Please note that MPS version 1.4 is required for a motherboard to support a secondary PCI bus without the need for a PCI bridge. If your operating system comes with support for MPS 1.4, you should change the setting from the default of 1.1 to 1.4. You also need to enable MPS 1.4 support if you need to make use of the secondary PCI bus on a motherboard that doesn't come with a PCI bridge. This is because only MPS 1.4 supports a bridgeless secondary PCI bus. You should only leave it as 1.1 only if you are running an older operating system that only supports MPS 1.1. According to Eugene Tan, Windows NT already supports MPS 1.4. Therefore, newer operating systems like Windows 2000 and Windows XP shouldn't have any problem supporting MPS 1.4. However, users of the ABIT BP6 motherboard and Windows 2000 should take note of a possible problem with the MPS version set to 1.4. Dan Isaacs reported that when you set the MPS version to 1.4 in the ABIT BP6, Windows 2000 will not use the second processor. So, if you encounter this problem, set the MPS Version Control For OS to 1.1. Processor number feature This feature is only valid if you are using a processor that features an embedded unique identification number. This infamous "feature" debuted in the Intel Pentium III processor and is mainly found only in that processor. If the BIOS of my notebook is correct, the Transmeta Crusoe processor may also support this feature. But most manufacturers have refrained from integrating such a "feature" in their processors. Even Intel has declined to add this feature to the Intel Pentium 4 processor. This feature will most probably not appear unless you are using an Intel Pentium III or Transmeta Crusoe processor. It gives you the ability to control whether the embedded identification number can be read by external programs or not. Enable this if your secure transactions require you to use such a feature. Otherwise, I would recommend that you disable this feature to safeguard your privacy. This is because the embedded identification number can be misused to track your online activities. Speed error hold This feature was designed to prevent accidental overclocking. This is very useful for novice users who want nothing to do with overclocking and yet may have inadvertently set the wrong processor speed in the BIOS. When enabled, this feature will check the processor clock speed at boot up and halt the booting process if the clock speed is different from the speed stated in the processor ID. It will also display an error message to warn you that the processor is running at the wrong speed. To correct the situation, you will have to enter the BIOS and correct the processor speed. Most BIOSes, however, will automatically reset the processor to the correct speed. All you have to do then is enter the BIOS, verify it and save the change. If you are thinking of overclocking the processor, you must disable this feature as it prevents the motherboard from booting up with an overclocked processor. Although this may seem really obvious, I have seen countless overclocking initiates puzzling over the error message whenever they try to overclock their processors. So, before you start pulling your hair and screaming hysterically that Intel or AMD has finally implemented a clock speed lock on their processors, try disabling this feature. ;-) Spread spectrum When the motherboard's clock generator pulses, the extreme values (spikes) of the pulses create EMI (Electromagnetic Interference). The Spead Spectrum feature reduces the EMI by modulating the pulses so that the spikes of the pulses are reduced to flatter curves. It does so by varying the frequency slightly so that the signal doesn't use any particular frequency for more than a moment. This reduces the amount of interference that will affect the other electronics in the area. The BIOS usually offers two different levels of modulation - 0.25% or 0.5%. That's the amount of modulation (or jitter) from the baseline signal. The greater the modulation, the greater the reduction of EMI. Therefore, if you need to significantly reduce EMI in the surrounding area, a modulation of 0.5% is recommended. In most conditions, frequency modulation via this feature shouldn't cause any problems. However, system stability may be slightly compromised in certain situations. For example, enabling Spread Spectrum may cause improper functioning of timing-critical devices like clock-sensitive SCSI devices. Spread Spectrum can also cause problems with overclocked systems, especially those that have been taken to extremes. The slight modulation of frequency may cause the processor or any other overclocked components of the system to fail, leading to very predictable consequences. Of course, this depends on the amount of modulation, the extent of overclocking and other factors like temperature variation, etc... As such, the problem may not readily manifest itself instantly. Therefore, it is recommended that you disable this feature if you are overclocking your system. The risk of crashing your system isn't worth the reduction in EMI. Of course, if EMI reduction is important to you, enable this feature by all means but reduce the clock speed a little to give this feature some "space" to modulate safely. If you are not overclocking, the decision to enable or disable this feature is really up to you. But if you ask me, unless you have EMI problems, it's best to disable this feature to remove the possibility of stability issues. Some BIOSes also offer a Smart Clock option. Instead of modulating the frequency of the pulses over time, Smart Clock turns off the AGP, PCI and SDRAM clock signals that are not in use. Thus, EMI can be reduced without compromising system stability. As a bonus, using Smart Clock also help to reduce power consumption. The degree of EMI and power reduction will depend on the number of free (empty) AGP, PCI and SDRAM slots. But generally, Smart Clock won't be able to reduce EMI as effectively as simple frequency modulation. Still, if your BIOS comes with this Smart Clock option, you should select it over the 0.25% or 0.5% options if you need some EMI reduction. It will allow you to reduce EMI without any risk of compromising stability. STORAGE SUBSYSTEM 32 bit disk access The name 32-bit Disk Access is actually a misnomer because it doesn't really allow 32-bit access to the hard disk. The IDE interface is always 16-bits in width even when the IDE controller is on the 32-bit PCI bus. What this feature actually does is command the IDE controller to combine two 16-bit reads from the hard disk into a single 32-bit double word transfer to the processor. This allows the PCI bus to be more efficiently used as the number of transactions required for a particular amount of data is effectively halved!
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Mr.X.'s TWEAKING AND OPTIMIZING WIN
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-Msdownld.tmp This one needs manual
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If you have Windows 95/NT you can e
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BootKeys=1 BootMenu=0 BootMenuDefau
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Settings\Cache\History] "CachePath"
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Similarly, open Internet Explorer,
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g - Restart your computer once step
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38. Keep IE crash free Here's a tip
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44. Switch off Dos memory manager D
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Data: D:\WIN95 58. Clear Recent Doc
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Click on the property tab for this
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Right-click in the right hand pane
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By the use of this client software,
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8. Want Real mode DOS back in Windo
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Recommendation: This service will f
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detect and/or recognize your hardwa
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It should almost certainly benefit
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Click start. click settings. click
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Click Analyze, click ok, click Acti
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Nonbrowser. A nonbrowser is configu
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Private IP Addressing (APIPA) for p
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provides protected storage for sens
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If the service is turned off, RIS i
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enables NetBIOS name resolution. Pr
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11. Adaptive Menus Microsoft Office
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3. Speed up Internet Explorer 6 Fav
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Note that in doing this, you are co
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claimed for a ‘fixed’ page file
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When a NTFS drive is formatted it b
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Goto above key in registry and you
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To get Admin account on the "Welcom
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is not acceptable, and that anythin
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Page 75 and 76: Alt - 0166 = ¦ Alt - 0167 = § Alt
Page 77 and 78: 11. Remove the default administrato
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Page 81 and 82: Right-click in the right hand pane,
Page 83 and 84: 57. Temporarily Assign Yourself Adm
Page 85 and 86: Install the appropriate post-Servic
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Page 89 and 90: Caution If your computer is not in
Page 91 and 92: C:\inetpub\ftproot (FTP server) C:\
Page 93 and 94: MBR Work - www.terabyteunlimited.co
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Page 109 and 110: Therefore, using the latest video B
Page 111 and 112: So, for optimal performance, you sh
Page 113 and 114: second clock cycle before sending t
Page 115 and 116: SDRam RAS precharge time This featu
Page 117 and 118: The shorter the delay, the earlier
Page 119: CPU level 1 cache The modern proces
Page 123 and 124: Please note that even if you don't
Page 125 and 126: Advanced Settings tab of the associ
Page 127 and 128: However, this is not a surefire way
Page 129 and 130: This feature allows you to manually
Page 131 and 132: doubling the bandwidth of the proce
Page 133 and 134: When this feature is enabled, the s
Page 135 and 136: VLink 8X support V-Link refers to V
Page 137 and 138: You will notice that the interrupts
Page 139 and 140: AMD OVERCLOCKING - changing the mul
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Page 145 and 146: Hard drive limitations Overclocking
Page 147 and 148: 5.0x 500Mhz 560Mhz 620Mhz 665Mhz 5.
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Page 153 and 154: Benchmarks allow you to measure you
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