Tweaking Optimizing Windows.pdf - GEGeek

However, this is not a surefire way of overclocking the CPU. Increasing it to the highest value will not necessarily mean that you can
overclock the CPU more than you already can. In addition, it is important to note that increasing the CPU drive strength will not
improve its performance. Contrary to popular opinion, it is not a performance enhancing feature.
Although little else is known about this feature, the downsides to a high CPU drive strength would probably be increased EMI
(Electromagnetic Interference), power consumption and thermal output. Therefore, unless you need to boost the processor bus
drive strength (for troubleshooting or overclocking purposes), it is recommended that you leave it at the default setting.
CPU to PCI post write
This feature controls the CPU-to-PCI write buffer. If this buffer is disabled, the processor writes directly to the PCI bus. Although it
may seem like the faster and better method, that isn't really true. Because the processor bus (which runs from 100MHz to 266MHz
and beyond) is many times faster than the PCI bus (33MHz), any CPU writes to the PCI bus will have to wait until the PCI bus is
ready to receive data. This prevents the processor from doing anything else until it has completed the transaction.
Enabling this feature allows the processor to immediately write up to four words of data to the CPU-to-PCI write buffer so that it can
move onto another task without waiting for those four words of data to be written to the PCI bus.
Now, the data in the write buffer won't reach the PCI bus any faster than usual. This is because they will only be written to the PCI
bus when the next available PCI cycle starts. But the difference here is that the entire operation can now occur without tying up the
processor.
To sum it all up, enabling the CPU to PCI write buffer frees up CPU cycles that would normally be wasted waiting for the PCI bus.
Therefore, it is recommended that you enable the CPU to PCI write buffer.
CPU to PCI write buffer
This feature controls the CPU-to-PCI write buffer. If this buffer is disabled, the processor writes directly to the PCI bus. Although it
may seem like the faster and better method, that isn't really true. Because the processor bus (which runs from 100MHz to 266MHz
and beyond) is many times faster than the PCI bus (33MHz), any CPU writes to the PCI bus will have to wait until the PCI bus is
ready to receive data. This prevents the processor from doing anything else until it has completed the transaction.
Enabling this feature allows the processor to immediately write up to four words of data to the CPU-to-PCI write buffer so that it can
move onto another task without waiting for those four words of data to be written to the PCI bus.
Now, the data in the write buffer won't reach the PCI bus any faster than usual. This is because they will only be written to the PCI
bus when the next available PCI cycle starts. But the difference here is that the entire operation can now occur without tying up the
processor.
To sum it all up, enabling the CPU to PCI write buffer frees up CPU cycles that would normally be wasted waiting for the PCI bus.
Therefore, it is recommended that you enable the CPU to PCI write buffer.
Delayed transaction
The ISA bus is slower than the PCI bus. So, when the PCI bus wants to write to the ISA bus, it has to wait until the ISA bus is
ready. Because the ISA bus is many, many times slower than the PCI bus, the PCI bus is normally stalled for a long time whenever
a PCI cycle to the ISA bus is initiated. This prevents other devices from accessing the PCI bus and can cause problems for timecritical
applications that need constant access to the PCI bus.
To prevent the PCI bus from stalling every time it tries to write to the ISA bus, many chipsets now come with an embedded 32-bit
posted write buffer. This buffer is designed to store PCI-to-ISA writes and thus allows delayed transaction cycles to be generated.
When enabled, the PCI bus immediately writes up to two 16-bit or four 8-bit data to the write buffer. The PCI bus can then be freed
to perform other transactions. The buffer contents are independently written to the ISA bus when it's ready. Now, the data in the
write buffer won't reach the ISA bus any faster than usual. This is because they will only be written to the ISA bus when the next
available ISA cycle starts. But the difference here is that the entire operation can now occur without tying up the PCI bus.
This BIOS feature controls the operation of that embedded 32-bit posted write buffer. If enabled, up to four bytes of PCI-to-ISA
writes are buffered and the PCI bus is released after writing to the buffer. If Delayed Transaction is disabled, the PCI bus will bypass
the write buffer and write directly to the ISA bus.
It's highly recommended that you enable this feature for better PCI performance and to meet PCI 2.1 specifications. Disable it only
if your PCI cards cannot work properly with this feature enabled or if you are using an ISA card that is not PCI 2.1 compliant. Note
that Delayed Transaction is only important if you are actually using ISA devices. It is of no consequence at all if you are not using
any ISA devices or if your motherboard doesn't even come with ISA slots!
Duplex selection
The Duplex Select option is usually found under the Onboard Serial Port 2 BIOS feature. It is slaved to the second serial port so if
you disable that serial port, this option will disappear from the screen or appear grayed out.
This feature allows you to determine the transmission mode of the IR port. Selecting Full-Duplex permits simultaneous two-way
transmission, like a conversation over the phone. On the other hand, selecting Half-Duplex only permits transmission in one
direction at any one time, which is more like a conversation over the walkie-talkie.
Naturally, the Full-Duplex mode is the faster and more desirable choice. You should use Full-Duplex if possible. Consult your IR
peripheral's manual to determine if it supports Full-Duplex transmission or not. The IR peripheral must support Full-Duplex for this
option to work.
ECP mode use DMA
This feature is usually found under the Parallel Port Mode feature. It's slaved to the ECP (Extended Capabilities Port) options of the
Parallel Port Mode feature so if you do not enable either ECP or ECP+EPP, this feature will disappear from the screen or appear
grayed out. The ECP mode uses the DMA protocol to achieve data transfer rates of up to 2.5Mbits/s and provides symmetric
bidirectional communication. This means it requires the use of a DMA channel.