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handbook of modern sensors

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5.4 Analog-to-Digital Converters 183<br />

discharging its capacitor through S 2 . The charge at the capacitor gained during the<br />

input signal integrate phase is precisely equal to the charge lost during the reference<br />

deintegration phase. Therefore, the following holds:<br />

V in<br />

T t<br />

= V ref , (5.33)<br />

R in C in R in C in<br />

which leads to<br />

V in<br />

= t<br />

V ref T . (5.34)<br />

Therefore, the ratio <strong>of</strong> the average input voltage and the reference voltage is replaced<br />

by the ratio <strong>of</strong> two time intervals. Then, the counter does the next step—it converts<br />

the time interval t into a digital form by counting the clock pulses during t. The<br />

total count is the measure <strong>of</strong> V in (remember that V ref and T are constants).<br />

The dual-slope converter has the same advantage as the charge-balance converter:<br />

They both reject frequencies 1/T corresponding to the integrate timing. It should be<br />

noted that selecting time T = 200 ms will reject noise produced by both 50 and 60 Hz,<br />

thus making the converter immune to the power line noise originated at either standard<br />

frequency. Further, the conversion accuracy is independent <strong>of</strong> the clock frequency<br />

stability, because the same clock sets timing T and the counter. The resolution <strong>of</strong> the<br />

conversion is limited only by the analog resolution; hence, the excellent fine structure<br />

<strong>of</strong> the signal may be represented by more bits than would be needed to maintain a given<br />

level <strong>of</strong> scale-factor accuracy. The integration provides rejection <strong>of</strong> high-frequency<br />

noise and averages all signal instabilities during the interval T . The throughput <strong>of</strong> a<br />

dual-slope conversion is limited to somewhat less than 1/2T conversions per second.<br />

To minimize errors produced in the analog portion <strong>of</strong> the circuit (the integrator and<br />

the comparator), a third timing phase is usually introduced. It is called an auto-zero<br />

phase because during that phase, the capacitor C in is charged with zero-drift errors,<br />

which are then introduced in the opposite sense during the integration, in order to<br />

nullify them. An alternative way to reduce the static error is to store the auto-zero<br />

counts and then digitally subtract them.<br />

Dual-slope converters are <strong>of</strong>ten implemented as a combination <strong>of</strong> analog components<br />

(OPAMs, switches, resistors, and capacitors) and a microcontroller, which<br />

handles the functions <strong>of</strong> timing, control logic, and counting. Sometimes, the analog<br />

portion is packaged in a separate integrated circuit. An example is the TS500 module<br />

from Texas Instruments.<br />

5.4.4 Successive-Approximation Converter<br />

These converters are widely used in a monolithic form thanks to their high speed (to 1<br />

MHz throughput rates) and high resolution (to 16 bits). The conversion time is fixed<br />

and independent <strong>of</strong> the input signal. Each conversion is unique, as the internal logic<br />

and registers are cleared after each conversion, thus making these A/D converters<br />

suitable for the multichannel multiplexing. The converter (Fig. 5.29A) consists <strong>of</strong><br />

a precision voltage comparator, a module comprising shifter registers and a control

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