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DigitalVideoAndHDTVAlgorithmsAndInterfaces.pdf

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SMPTE 260M describes a scheme,<br />

now deprecated, to convey line<br />

numbers in ANC packets where<br />

DID=0. That value is now “undefined.”<br />

Two types of ANC packet are differentiated by bit 7 of<br />

the DID word. If DID 7 is asserted, the packet is Type 1;<br />

DID is followed by data block number (DBN). There are<br />

128 DID codes available for Type 1 packets. The DBN<br />

value indicates continuity: If zero, it is inactive; otherwise,<br />

it counts packets within each DID from 1 through<br />

255, modulo 255.<br />

If DID 7 is negated, the packet is Type 2: The DID is<br />

followed by a secondary data ID (SDID), giving<br />

127 · 255 (i.e., 32385) ID codes for Type 2 packets.<br />

Three DID values, 004 h , 008 h , and 00C h indicate<br />

a Type 2 ANC packet coded with 8-bit data; other DID<br />

values in the range 001 h through 00F h are prohibited.<br />

DID 80 h marks a packet for deletion. DID 84 h marks<br />

the last ANC packet in a VANC or HANC region.<br />

The data count (DC) word contains a value from 0<br />

through 255 (protected by two parity bits), indicating<br />

the count of words in the user data area. The DC word<br />

spans all ten bits of the interface. Even if an 8-bit DID is<br />

indicated, SMPTE standards imply that the two least<br />

significant bits of the DC word are meaningful. (If they<br />

were not, then the count of user data words could not<br />

be uniquely determined.)<br />

The checksum (CS) word provides integrity checking for<br />

the contents of an ancillary packet. In every word from<br />

DID through the last word of UDW, the MSB is masked<br />

out (to zero); these values are summed modulo 512.<br />

The 9-bit sum is transmitted in bits 8 through 0 of CS;<br />

bit 9 is coded as the complement of bit 8.<br />

SDI coding<br />

In the obsolete Rec. 656 parallel interface that<br />

I mentioned on page 128, a dedicated clock accompanied<br />

the data. In the serial interface it is necessary for<br />

a receiver to recover the clock from the coded<br />

bitstream. The coded bitstream must therefore contain<br />

significant power at the coded bit rate. Coaxial cable<br />

attenuates high-frequency information; equalization is<br />

necessary to overcome this loss. Because equalizers<br />

involve high-frequency AC circuits, the coded bitstream<br />

396 DIGITAL VIDEO AND HDTV ALGORITHMS AND INTERFACES

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