Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

5.3.3 Performance Event Selection
Performance event selection is critical to the success of performance counter-driven
power models. To identify a minimum set of representative performance events, the
relationship between each event and power consumption must be understood. This
section describes the performance monitoring counter events used to construct the trickle-
down power model. The definition and insight behind selection of the counters is
provided.
Fetched µops – Micro-operations fetched. Comparable to the Pentium IV fetched micro-
operations, this metric is highly correlated to processor power. It accounts for the largest
portion of core pipeline activity including speculation. This is largely the result of fine-
grain clock gating. Clocks are gated to small portions of the pipelines when they are not
being used.
FP µops Retired – Floating point micro-operations retired. FP µops Retired accounts
for the difference in power consumption between floating point and integer instructions.
Assuming equal throughput, floating point instructions have significantly higher average
power. Ideally, the number of fetched FPU µops would be used. Unfortunately, this
metric is not available as a performance counter. This is not a major problem though
since the fetched µops metric contains all fetched µops, integer and floating point.
DC Accesses – Level 1 Data Cache Accesses. A proxy for overall cache accesses
including Level 1,2,3 data and instruction. Considering the majority of workloads, level
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