Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

system memory for DMA access. Similarly interrupts from multiple devices can be
distinguished by interrupt number or address in the case of message signaled interrupts.
CPU
Chipset Memory
I/O
Disk Network
Figure 5.1. Propagation of Performance Events
With over forty detectable performance events [Sp02], the Pentium IV provides a
challenge in selecting events that are most representative of subsystem power. The
subsystem interconnections pictured in Figure 5.1 provide a starting point. By noting the
“trickle-down” effect of events in the processor, a subset of the performance events is
selected to accurately model subsystem power consumption. A simple example would be
the effect of cache misses in the processor. For a typical microprocessor the top-level
cache affects power consumption in the memory subsystem. Transactions that cannot be
satisfied (cache miss) by the top-level cause a cache line (block) sized access to the main
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L3 Miss
TLB Miss
DMA Access
MemBus Access
Uncacheable Access
I/O Interrupt