Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

Temperature is controlled by adjusting the speed of the processor’s fan. Temperature is
observed with a 1 /8 degree Celsius resolution using an on-die temperature sensor [Bk09].
This sensor can be accessed by the system under test through a built-in, on-chip register.
The resultant temperature-dependent leakage equation is shown in Table 3.9. Since
temperature is modeled over only the operating range of the processor, it can be
accounted for as a quadratic equation. Alternatively, a wider temperature range can be
accounted for using and an exponential equation in the form of a×e T×b . The coefficients a
and b are found through regression. The term T represents the die temperature in Celsius.
For this study the quadratic form is used due to its lower computational overhead and
sufficient accuracy. Voltage is controlled using the P-State Control Register [Bk09].
This allows selection of one of five available voltage/frequency combinations. Voltage is
observed externally as a subset of the traced power data. Like the workload dependent
model, the coefficients of the static power model are tuned using regression techniques.
Note that the static power model is highly process dependent. Processors with different
semiconductor process parameters require the model to be re-tuned.
The dominant power management effects (voltage/frequency scaling, clock gating) are
further accounted for using the gateable and ungateable power models. Gateable power
is found by measuring the effect of enabling/disabling idle core clock gating. Ungateable
represents the portion of power which cannot be gated. These components are also found
experimentally. The resultant, average error in the model is 0.89%. The standard
deviation of the error for SPEC CPU2006 and SYSmark 2007 is less than 1%. Worst-
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