Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

Chapter 6 Performance Effects of
Dynamic Power Management
6.1 Direct and Indirect Performance Impacts
6.1.1 Transition Costs
Due to physical limitations, transitioning between adaptation states may impose some
cost. The cost may be in the form of lost performance or increased energy consumption.
In the case of DVFS, frequency increases require execution to halt while voltage supplies
ramp up to their new values. This delay is typically proportional to the rate of voltage
change (seconds/volt). Frequency decreases typically do not incur this penalty as most
digital circuits will operate correctly at higher than required voltages. Depending on
implementation, frequency changes may incur delays. If the change requires modifying
the frequency of clock generation circuits (phase locked loops), then execution is halted
until the circuit locks on to its new frequency. This delay may be avoided if frequency
reductions are implemented using methods which maintain a constant frequency in the
clock generator. This is the approach used in Quad-Core AMD processor c-state
implementation. Delay may also be introduced to limit current transients. If a large
number of circuits all transition to a new frequency, then excessive current draw may
result. This has a significant effect on reliability. Delays to limit transients are
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