Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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Vardan [MaVa04] perform a subsystem level power study of a Pentium M laptop. They present average power results for productivity workloads. In contrast, this dissertation considers a server-class SMP running a commercial workload. Feng [FeGe05-1] performs a study on a large clustered system running a scientific workload. As part of a proposed resource management architecture, Chase [ChAn01] presents power behavior at the system level. Lacking in all of these studies is a consideration of power phase duration. Duration is a critical aspect since it directs power adaptions. An effective adaptation scheme must choose adaptations that are appropriate to the expected duration of the event. For example, since there is a performance and energy cost associated with DVFS, changes to voltage/frequency should only be performed if the system can amortize those costs before the next change is required. 8.3 Predictive Power Adaptation While most existing power management schemes are reactive, there are a few related proposals that use predictive power management [IsBu06] [DuCa03] [DiSo08]. Isci [IsBu06] uses table-based predictors of memory operations/instruction, to direct DVFS decisions for single-threaded workloads. Duesterwald et al. [DuCa03] examine table- based predictor techniques to predict performance-related metrics (IPC, cache misses/instruction and branch misprediction rates) of single-thread workloads, but not power. Diao [DiSo08] uses machine learning to predict activity patterns. The predictions are used to make policy decisions for entering core idle states. In contrast the 150
prediction scheme in this dissertation makes use of table-based prediction structures and the repetitive nature of power phases to predict performance demand and/or power consumption. Further, the validation of the predictor is performed using realistic, representative workloads. These workloads contain complex power management events that are not present in the simple workloads used in the contemporary research. These events are critical to a practical power management schemed since they induce power and performance effects larger than those seen in simple workloads. Outside the predictive adaptation realm, there are numerous proposals for increasing energy efficiency and staying within operating limits. To increase energy efficiency studies have applied adaptation at the processor level [LiMa06] [LiBr05] [WuJu05] [Vi07] [PaSt06] [KoGh05] [KoDe04] and system level [MeGo09] [RaLe03] [BoEl02]. To stay within defined operating limits studies have applied adaptation at the processor level [HaKe07] [RaHa06] [ChJa09] [IsBu06] [McPo06] and complete system level [LeWa07] [RaLe06] [ChDa05] [ChAn01] [Po10] [FaWe07] [WaCh08] [MiFr02]. 8.4 Deadline and User-Driven Power Adaptation In the embedded and real-time computing domains power management is performed under a different set of requirements. Rather than focusing on reduction of average or peak power, computation deadlines are more critical. These systems contain various components and processes with critical deadlines for computation. For example, network devices implement buffers to allow the network interface to queue transactions. This 151
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Power (Watts) 30 25 20 15 10 5 0 Co
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workloads become more memory-bound,
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At the other extreme, the productiv
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
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average access time to the distant
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Watts Figure 5.6 Disk Power Model (
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exhibits little variation in power
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The memory model averaged about 9%
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efficiency rather than performance.
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through the application GUI. The nu
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1 data cache access rate dominates
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periods of disconnect, cache snoop
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5.3.4 CPU To test the extensibility
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Despite this, high accuracy of less
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Light activity yields higher precha
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Page 175 and 176: [BiJo06-1] W. L. Bircher and L. Joh
Page 177 and 178: the 2005 ACM SIGMETRICS Internation
Page 179 and 180: [HaKe07] H. Hanson, S.W. Keckler, K
Page 181 and 182: [JoMa01] R. Joseph and M. Martonosi
Page 183 and 184: [LiBr05] Y. Li, D. Brooks, Z. Hu, a
Page 185 and 186: [Os06] Open Source Development Lab,
Page 187 and 188: [WaCh08] X. Wang and M. Chen. Clust
Page 189 and 190: [PiSh01] P. Pillai and K. G. Shin.
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