Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

prefetch traffic does increase after the model failure, the total number of bus transactions
does not. Since the number of bus transactions generated by each processor does not
sufficiently predict memory power, an outside (non-CPU) agent is accessing the memory
bus. For the target system the only other agent on the memory bus is the memory
controller itself, performing DMA transactions on behalf of I/O devices.
Bus Transactions/1K Cycles
30
25
20
15
Cache-Miss model error grows as
memory traffic becomes dominated
by prefetch
Figure 5.4 Prefetch and Non-Prefetch Bus Transactions – mcf
Changing the model to include memory accesses generated by the microprocessors and
DMA events resulted in a model that remains valid for all observed bus utilization rates.
It should be noted that using only the number of read/write accesses to the DRAM does
not directly account for power consumed when the DRAM is in the precharge state.
DRAM in the precharge state consumes more power than in idle/disabled state, but less
than in the active state. During the precharge state, data held in the sense amplifiers is
committed to the DRAM array. Since the initiation of a precharge event is not directly
controlled by read/write accesses, precharge power cannot be directly attributed to
75
100%
50%
10
5
Non-Prefetch
Prefetch
-50%
0
Error
-100%
0 50 100
Seconds
150 200
0%
Error(%)