Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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3.8% due to limited frequency scaling of the workload (70%) and reduced total time in the active state. 6% Residency 0% 6% Residency 0% 6% Residency 0% 6% Residency 0% Scheduling Quantum 16ms E-Learning Video Creation Productivity 1 10 100 1000 Phase Length (ms) Figure 7.7 Core-Level Phase Length Probability Distributions Next, power savings is considered. Though it is possible to bias a reactive DVFS algorithm to achieve performance comparable to a predictive algorithm, it is not possible to do so without increasing power consumption drastically. Prediction allows DVFS selection to select the “correct” frequency for both performance and power savings. 3D 140 DVFS Change Interval 100ms
Table 7.6: SYSmark 2007 Power and Performance Impact of PPPP Predictive (PPPP) E-Learning Productivity 141 Reactive (Vista) Predictive (PPPP) Reactive (Vista) Power (W) 16.6 18.2 14.3 15.1 Power Savings 8.3% 5.3% Delay (sec) 924 963 585 607 Speedup 4.2% 3.7% Energy (KJ) 15.4 17.5 8.4 9.2 Energy x Delay(KJs) 14.2×10 3 16.9×10 3 4.9×10 3 5.6×10 3 Energy x Delay(KJs 2 ) 13.2×10 6 16.2×10 6 2.9×10 6 3.4×10 6 Energy Savings 12.3% 8.7% Video Creation 3D Predictive (PPPP) Reactive (Vista) Predictive (PPPP) Reactive (Vista) Power (W) 18.6 19.5 25.9 26.6 Power Savings 4.7% 2.9% Delay (sec) 1129 1172 548 568 Speedup 3.8% 3.6% Energy (KJ) 20.9 22.8 14.2 15.1 Energy x Delay(KJs) 23.6×10 3 26.7×10 3 7.8×10 3 8.6×10 3 Energy x Delay(KJs 2 ) 26.7×10 6 31.3×10 6 4.3×10 6 4.9×10 6 Energy Savings 8.2% 6.3%
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Power (Watts) 30 25 20 15 10 5 0 Co
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workloads become more memory-bound,
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At the other extreme, the productiv
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
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average access time to the distant
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Watts Figure 5.6 Disk Power Model (
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exhibits little variation in power
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The memory model averaged about 9%
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efficiency rather than performance.
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through the application GUI. The nu
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Page 109 and 110: 5.3.4 CPU To test the extensibility
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Page 113 and 114: Light activity yields higher precha
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Page 119 and 120: Chapter 6 Performance Effects of Dy
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Page 125 and 126: 6.1.5 Direct Performance Effects Si
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Page 141 and 142: 7.2 Commercial DVFS Algorithm Exist
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Page 151 and 152: First, prediction accuracy is consi
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Page 169 and 170: Chapter 9 Conclusions and Future Wo
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Page 175 and 176: [BiJo06-1] W. L. Bircher and L. Joh
Page 177 and 178: the 2005 ACM SIGMETRICS Internation
Page 179 and 180: [HaKe07] H. Hanson, S.W. Keckler, K
Page 181 and 182: [JoMa01] R. Joseph and M. Martonosi
Page 183 and 184: [LiBr05] Y. Li, D. Brooks, Z. Hu, a
Page 185 and 186: [Os06] Open Source Development Lab,
Page 187 and 188: [WaCh08] X. Wang and M. Chen. Clust
Page 189 and 190: [PiSh01] P. Pillai and K. G. Shin.
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