Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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Temperature is controlled by adjusting the speed of the processor’s fan. Temperature is observed with a 1 /8 degree Celsius resolution using an on-die temperature sensor [Bk09]. This sensor can be accessed by the system under test through a built-in, on-chip register. The resultant temperature-dependent leakage equation is shown in Table 3.9. Since temperature is modeled over only the operating range of the processor, it can be accounted for as a quadratic equation. Alternatively, a wider temperature range can be accounted for using and an exponential equation in the form of a×e T×b . The coefficients a and b are found through regression. The term T represents the die temperature in Celsius. For this study the quadratic form is used due to its lower computational overhead and sufficient accuracy. Voltage is controlled using the P-State Control Register [Bk09]. This allows selection of one of five available voltage/frequency combinations. Voltage is observed externally as a subset of the traced power data. Like the workload dependent model, the coefficients of the static power model are tuned using regression techniques. Note that the static power model is highly process dependent. Processors with different semiconductor process parameters require the model to be re-tuned. The dominant power management effects (voltage/frequency scaling, clock gating) are further accounted for using the gateable and ungateable power models. Gateable power is found by measuring the effect of enabling/disabling idle core clock gating. Ungateable represents the portion of power which cannot be gated. These components are also found experimentally. The resultant, average error in the model is 0.89%. The standard deviation of the error for SPEC CPU2006 and SYSmark 2007 is less than 1%. Worst- 38
case error is 3.3%. Alternatively stated, 68.2% of workloads have an error of less than 1%. Per workload error is shown in Figure 3.4. The composition of the CPU model is summarized in Table 3.9. Watts Table 3.9 AMD Quad-Core Power Model Power Models Equation Total Power ∑ (WorkloadDependentN + UngateableN + GateableN) 37 36 35 34 33 32 31 30 Workload Dependent Power Idle Power Management Power (Gateable) Irreducible Power (Ungateable) Irreducible Power (Static) 1.4% 1.4% 3.0% 0.6% 0.4% 0.8% + StaticVolt,Temp ((FetchOpsN/Sec)×CoeffF+(FloatPointOpsN/Sec) ×CoeffFP +(DCAccessN/Sec) ×CoeffDC) ×Voltage 2 0.4% (%HaltedN) ×CoeffGateable×Voltage 2 ×FrequencyN (%NonHaltedN) ×CoeffUngateable×Voltage 2 ×FrequencyN 0.2% (Temp 2 ×CoeffT 2 +Temp 1 ×CoeffT 1 +×CoeffT 0 )VoltageN 2.1% 0.5% 0.3% 0.2% 0.9% 0.6% Error % Measured Modeled 0.3% 0.5% Figure 3.4 CPU Power Model – SPEC CPU 2006 Power and Average Error 39 0.6% 2.3% 0.2% 1.0% 1.6% 0.2% 0.9% 0.2% 0.2% 3.3% 0.6% 3.5% 3.0% 0.8% 0.1% perlbench bzip2 gcc mcf gobmk hmmer sjeng libquantum h264ref omnetpp astar xalancbmk bwaves gamess milc zeusmp gromacs cactusADM leslie3d namd dealII soplex povray calculix GemsFDTD tonto lbm wrf sphinx3 2.5% 2.0% 1.5% 1.0% 0.5% 0.0%
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Copyright by William Lloyd Bircher
Page 3 and 4: Predictive Power Management for Mul
Page 5 and 6: Acknowledgements I would like to th
Page 7 and 8: Predictive Power Management for Mul
Page 9 and 10: Table of Contents Chapter 1 Introdu
Page 11 and 12: 5.3.6 Memory ......................
Page 13 and 14: List of Tables Table 1.1 Windows Vi
Page 15 and 16: List of Figures Figure 1.1 CPU Core
Page 17 and 18: Chapter 1 Introduction Computing sy
Page 19 and 20: increases the overhead of adaptatio
Page 21 and 22: suboptimal from a power and perform
Page 23 and 24: Active Core Activity Idle except fo
Page 25 and 26: 4. Design a predictive power manage
Page 27 and 28: 1.7 Organization This dissertation
Page 29 and 30: Chapter 2 Methodology The developme
Page 31 and 32: 2.1.2 Subsystem-Level Power in a Se
Page 33 and 34: The main components are subsystem p
Page 35 and 36: Table 2.4 Laptop System Description
Page 37 and 38: 2.3 Performance Counter Sampling To
Page 39 and 40: instruction streams that exercise a
Page 41 and 42: the power trace to the PMC trace co
Page 43 and 44: The first bar in Figure 3.1 “Fetc
Page 45 and 46: Table 3.4 Instruction Linear Regres
Page 47 and 48: long time to complete, more aggress
Page 49 and 50: power adaptations as c-states. Thes
Page 51 and 52: Core Power (Watts) 60 50 40 30 20 1
Page 53: The difference between C0-Idle and
Page 57 and 58: 3. Based on basic domain knowledge,
Page 59 and 60: 3.6 Summary This section describes
Page 61 and 62: Power (Watts) 30 25 20 15 10 5 0 Co
Page 63 and 64: workloads become more memory-bound,
Page 65 and 66: At the other extreme, the productiv
Page 67 and 68: processor. In both platforms the to
Page 69 and 70: Table 4.1 Subsystem Power Standard
Page 71 and 72: the case of I/O, the observed workl
Page 73 and 74: average distribution. The apparent
Page 75 and 76: Table 4.4 Workload Phase Classifica
Page 77 and 78: Frequency 1 10 100 1000 PhaseLength
Page 79 and 80: power management, it is shown that
Page 81 and 82: power measurement hardware for mult
Page 83 and 84: memory. Since the number of main me
Page 85 and 86: TLB Misses - Loads/stores that miss
Page 87 and 88: The form of the subsystem power mod
Page 89 and 90: 5.2.2 Memory This section considers
Page 91 and 92: prefetch traffic does increase afte
Page 93 and 94: average access time to the distant
Page 95 and 96: Watts Figure 5.6 Disk Power Model (
Page 97 and 98: exhibits little variation in power
Page 99 and 100: The memory model averaged about 9%
Page 101 and 102: efficiency rather than performance.
Page 103 and 104: through the application GUI. The nu
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1 data cache access rate dominates
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periods of disconnect, cache snoop
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5.3.4 CPU To test the extensibility
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Despite this, high accuracy of less
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Light activity yields higher precha
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5.3.8 Chipset The Chipset power mod
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applied to the GPU core logic, larg
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Chapter 6 Performance Effects of Dy
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can be considered as predictors whi
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improvement for low idle core frequ
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6.1.5 Direct Performance Effects Si
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of SPEC CPU2000 workloads, almost n
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adjusting a hysteresis timer. The t
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increase/decrease time. Since the i
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In order to reduce p-state performa
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performance loss and power consumpt
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eactive scheme used in Windows Vist
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Watts Watts Watts Watts Watts 150 1
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7.2 Commercial DVFS Algorithm Exist
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of idle-active transitions in the c
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workload/operating systems adds and
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instructions. In APCI[Ac07] termino
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confidence level will drop below a
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First, prediction accuracy is consi
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coverage of 43% and accuracy over 9
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which corresponds to the DVFS sched
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Table 7.6: SYSmark 2007 Power and P
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In this case the predictor achieves
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2007 power consumption contains man
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
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[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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