Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

The memory model averaged about 9% error across all workloads. Surprisingly the
memory model fared better under integer workloads. The error rate for floating point
workloads tended to be highest for workloads with the highest sustained power
consumption. For these cases the model tends to underestimate power. Since the rate of
bus transactions is similar for high and low error rate workloads it is suspected that the
cause of underestimation is the access pattern. In particular the model does not account
for differences in the power for read versus write access. Also, the number of active
banks within the DRAM is not directly accounted for. Accounting for the mix of reads
versus writes would be a simple addition to the model. However, accounting for active
banks will likely require some form of locality metric.
Idle power error is low for all cases indicating a good match for the DC term in the
models. Chipset error is high considering the small amount of variation. This is due to
the limitation of the constant model assumed for chipset power.
Table 5.2 Floating Point Average Model Error
Workload CPU Chipset Memory I/O Disk
Art 9.65% 5.87% 8.92% 0.240% 1.90%
Lucas 7.69% 1.46% 17.5 % 0.245% 0.31%
Mesa 5.59% 11.3% 8.31% 0.334% 0.17%
mgrid 0.360% 4.51% 11.4% 0.365% 0.55%
wupwise 7.34% 5.21% 15.9% 0.588% 0.42%
FP Average
6.13% 5.67% 12.41% 0.354% 0.67%
All Workload
Average
±3.53%
6.67 %
±3.42%
±3.57%
5.97%
±4.23%
83
±4.13%
8.80%
±5.54%
±0.142%
0.824%
±1.52%
±0.70%
0.39%
±0.49%