Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

adjusting a hysteresis timer. The timer specifies how long the processor remains at the
increased frequency before returning to the power saving mode. The results are shown in
Figure 6.3. The blue line represents the performance loss due to slow idle cores caused
by the application of c-states only. Like the p-state experiments, performance loss
reaches a clear breakpoint. In this case, the breakover point represents 40 percent of the
maximum architected delay. Coupling c-states with p-states, the red shows that the
breakover point is not as distinct since significant performance loss already occurs. Also,
like the p-state experiments, setting the hysteresis timer to a value of the breakover point
increases performance significantly while increasing power consumption only slightly.
Performance
100%
80%
60%
40%
20%
0%
0% 20% 40% 60% 80% 100%
C-State Hysteresis (%Max)
Figure 6.3 C-state vs. P-state Performance
Next, the effect of operating system tuning parameters for power adaptation selection is
considered. In order to demonstrate the impact of slow p-state selection, Figure 6.4 is
presented. The effect is shown by varying a single OS parameter while running the
SYSmark E-Learning subtest. In this graph, the TimeCheck value is varied from 1 ms to
1000 ms. TimeCheck controls how often the operating system will consider a p-state
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C-State Only
P-State+C-State