Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

periods of disconnect, cache snoop traffic and interrupts are blocked. This allows power
to be saved in the CPU I/O interconnect and I/O subsystem. Also, the DRAM may be
placed in self-refresh mode since DRAM access is blocked. If a cache snoop or interrupt
event occurs, the links are reconnected.
Spindle Active % – Percent time hard disk spindle is spinning. In traditional
mechanical hard drives, the spindle motor represent the largest single consumer of power
in the drive. To save energy the spindle motor can be powered down. Due to the high
latency (and energy consumption) for starting/stopping the spindle this can only be done
when the drive is expected to be idle for a long time (minutes or more). In practice,
typical workloads prevent the spindle from ever powering down. This includes all
benchmarks used in this study, except idle. Therefore, spindle activity can be sufficiently
accounted for by only distinguishing between idle and active workloads.
CPUToIOTransactions – Non-cacheable access to memory-mapped I/O devices . I/O
device activity can be approximated using a measure of how many memory transactions
generated by the CPUs are targeted at non-cacheable address space. Typically, I/O
devices contain a DMA controllers which performs access to cacheable space in system
memory. The configuration and control of these transactions is performed by the CPU
through small blocks of addresses mapped in non-cacheable space to each I/O device.
DRAMActive% – Percent time DRAM channel is active. Power savings in the DRAM
and memory controller is controlled by the memory controller. When a memory channel
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