Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

processor. In both platforms the top-level cache is contained in the chipset power rail.
To reduce power consumption and cost the desktop designer lacks an L3 cache.
Yet another subsystem with order-of-magnitude power reduction is the DRAM memory.
Despite higher operating frequency (533Mhz vs 100MHz) average DRAM power is
reduced by almost a factor of 10. The reason is reduced memory voltage (2.8V vs 1.5V),
reduced capacity (8GB vs 4GB) and more aggressive memory power management. Note
that the desktop system differentiates between DRAM, “Memory” subsystem and the
Memory Controller. The server system includes both in the memory subsystem. The
desktop memory controller has a similar level of power variation as the DRAMs. This is
due to the memory controller management power savings for both subsystems. This also
allows implementation of simple trickle-down models in multiple subsystems that are
driven by the same performance metrics.
An additional subsystem, not present in the server analysis is the RS780 GPU (graphics
processing unit). This subsystem has unique bi-modal power consumption. In all cases
GPU power is either near the maximum or minimum levels. For workloads with little or
no GPU activity power ranged from 0.8W to 1.3W with little variation. The graphics-
centric workloads of 3DMark06 had much greater variation as the workload alternates
between ~1W and 4W. This gives the GPU one of the largest power variations with a
standard deviation covering over 25% of the maximum power. The bimodal power
consumption is caused by aggressive idle power management and low active power
variation.
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