Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

In order to reduce p-state performance loss, the idle core frequency is set to 1250 MHz.
To prevent c-state performance loss, ramped probe mode is used with the hysteresis time
set above the breakover point. Also, C1e mode is disabled to prevent obscuring the idle
power savings of the architected p-states and c-states. The C1e state is a
microarchitectural feature that reduces power when all cores are idle. The power and
performance effects of this state can reduce the measureable effect of the p-state and c-
state decisions made by the operating system.
Two important findings are made regarding adaption settings. First, setting power
adaptations in consideration of performance bottlenecks reduces performance loss while
retaining power savings. Second, reducing OS p-state transition time increases
performance and power savings. Table 6.2 shows the resultant power and performance
for a range of OS p-state algorithm settings. It is shown that performance loss can be
limited to less than 10 percent for any individual subtest while power savings average 45
percent compared to not using power adaptations. The effect of workload characteristics
is evident in the results. E-learning and productivity show the greatest power savings due
to their low utilization levels. These workloads frequently use only a single core. At the
other extreme, 3D and video creation have less power savings and a greater dependence
on adaption levels. This indicates that more parallel workloads have less potential benefit
from p-state and c-state settings, since most cores are rarely idle. For those workloads,
idle power consumption is more critical. These results also point out the limitation of
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