Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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5.3.7 Memory Controller Since the memory controller is responsible to entry and exit of power saving modes for itself and memory, the memory metrics can also be used to estimate memory controller power. Though both use link active and DCTAccesses the relative weights are different. Memory power has a large sensitivity to the transaction rate, 4 · 10 -8 W/transaction/sec. Compare this to the memory controller which is more than four times smaller at 9 · 10 -9 W/transaction/sec. Similarly, transaction-independent portion is much higher for the memory controller at 1.9W compared to 0.98W for memory. This reflects the unmanaged power consumers in the memory controller. The same 3DMark06 error outliers exist here. An example of model versus measured Memory Controller power for 3DMark06-HDR1 is provided in Figure 5.9. The modeled power is provided below in Equation 5.9. Watts 3.0 2.5 2.0 1.5 Memory Controller Power = 9x10 -9 x DCTAccess/sec + 0.798 x LinkActive% + 1.05 Figure 5.9 Memory Controller Power (∑DCT Access, LinkActive) – HDR1 98 100% 50% 1.0 0.5 Measured Modeled Error -50% 0.0 -100% 0 20 40 Seconds 60 80 100 0% Error(%) (5.9)
5.3.8 Chipset The Chipset power model represents power consumed in the Hypertransport controller. Like the memory and memory controller subsystems, power consumption is dominated by the link disconnect state and memory controller accesses. Overall and worst-case were less than the others due to the workload independent contributions being relatively the largest. The model for I/O controller power is shown in Equation 5.10. 5.3.9 Disk I/O Controller Power = -10 -16 x (DCTAcc/sec) 2 + 2x10 -8 x (DCTAcc/sec) + 1.24 x LinkAct% + 1.34 The improvements in power management for hard disks between the server-class used in the Server study study [BiJo06-1] and the more recent desktop/mobile disk used here is evident in the power model in Equation 5.11. Rather than the negligible power variation previously observed (
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Power (Watts) 30 25 20 15 10 5 0 Co
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Page 69 and 70: Table 4.1 Subsystem Power Standard
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Page 75 and 76: Table 4.4 Workload Phase Classifica
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Page 81 and 82: power measurement hardware for mult
Page 83 and 84: memory. Since the number of main me
Page 85 and 86: TLB Misses - Loads/stores that miss
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Page 89 and 90: 5.2.2 Memory This section considers
Page 91 and 92: prefetch traffic does increase afte
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Page 95 and 96: Watts Figure 5.6 Disk Power Model (
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Page 99 and 100: The memory model averaged about 9%
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Page 103 and 104: through the application GUI. The nu
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Page 109 and 110: 5.3.4 CPU To test the extensibility
Page 111 and 112: Despite this, high accuracy of less
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Page 117 and 118: applied to the GPU core logic, larg
Page 119 and 120: Chapter 6 Performance Effects of Dy
Page 121 and 122: can be considered as predictors whi
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Page 125 and 126: 6.1.5 Direct Performance Effects Si
Page 127 and 128: of SPEC CPU2000 workloads, almost n
Page 129 and 130: adjusting a hysteresis timer. The t
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Page 133 and 134: In order to reduce p-state performa
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Page 141 and 142: 7.2 Commercial DVFS Algorithm Exist
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Page 147 and 148: instructions. In APCI[Ac07] termino
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Page 151 and 152: First, prediction accuracy is consi
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Page 157 and 158: Table 7.6: SYSmark 2007 Power and P
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Page 163 and 164: Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
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[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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