Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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Residency(%) 100 90 80 70 60 50 40 30 20 10 0 2 2 86 86 82 81 75 73 77 68 5 2 3 3 52 41 35 22 5 8 3 4 9 9 9 11 4 2 17 4 5 4 3 9 10 12 26 20 46 5 6 2 5 5 4 4 3 3 2 10 28 10 7 5 10 14 6 2 7 6 5 13 12 9 5 3 19 29 14 14 34 24 4 11 30 5 7 11 3 4 16 32 30 34 18 44 69 54 61 64 58 83 78 64 46 23 24 26 10 7 16 16 50 14 56 31 9 povray-rtr1 povray sandra_proc_arith TrueCrypt sandra_proc_memBW PdnBench2 sandra_proc_mmedia PdnBench1 cinebench1 3dmark06-cpu1 3dmark06-cpu2 WinRar pcmarkvantage itunes-mp3 Figure 7.3: Six-Core Phenom 2 Desktop Activity Levels Figure 7.4 takes the active-idle analysis of SYSmark to a deeper level by showing the core activity level within each subtest. Unlike traditional scientific and computing benchmarks, core activity level varies greatly over time. The primarily single-thread E- Learning and Productivity subtests are composed of single core active phases interspersed with all cores idle. The frequent transitions between active and idle make power management decisions difficult. Reacting too quickly to idle phases can induce excessive performance loss as code execution is halted to allow transition of clocks, voltage planes or component state. At the other extreme the 3D and Video Creation workloads have large sections of all cores being active. These regions, also interspersed with all-idle and one-active regions are critical for power sharing strategies. As the 128 SYSMark-3D 3dmark-vantage 3dmark06-gt2 3dmark06-hdr2 3dmark06-hdr1 photoshop-elements itunes-acc 3dmark06-gt1 SYSMark-VC SYSMark-EL SYSMark-PR All Idle 1 Active 2 Active 3 Active 4 Active 5 Active 6 Active
workload/operating systems adds and removes threads from cores the resultant power level changes drastically. The power difference between cores in the active versus idle state is much greater than differences within the active state. Active Cores Active Cores Active Cores Active Cores 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 Photoshop Illustrator Flash E-Learning Figure 7.4: Utilization of Multiple Cores by SYSmark 2007 Benchmark The effect of these frequent transitions on power and performance is significant. Bircher et al [BiJo08] show that the slow reaction of the Vista DVFS algorithm leads to a performance loss of 6%-10% for SYSmark 2007. It is shown that this performance loss is due to a large portion of the benchmark operating at DVFS state with frequencies as 129 Time Video Creation Time Productivity Outlook Excel 3dsMax Photoshop 3D After Effects Time Time Photoshop Flash Media Encode Sketchup
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Power (Watts) 30 25 20 15 10 5 0 Co
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workloads become more memory-bound,
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At the other extreme, the productiv
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
Page 93 and 94: average access time to the distant
Page 95 and 96: Watts Figure 5.6 Disk Power Model (
Page 97 and 98: exhibits little variation in power
Page 99 and 100: The memory model averaged about 9%
Page 101 and 102: efficiency rather than performance.
Page 103 and 104: through the application GUI. The nu
Page 105 and 106: 1 data cache access rate dominates
Page 107 and 108: periods of disconnect, cache snoop
Page 109 and 110: 5.3.4 CPU To test the extensibility
Page 111 and 112: Despite this, high accuracy of less
Page 113 and 114: Light activity yields higher precha
Page 115 and 116: 5.3.8 Chipset The Chipset power mod
Page 117 and 118: applied to the GPU core logic, larg
Page 119 and 120: Chapter 6 Performance Effects of Dy
Page 121 and 122: can be considered as predictors whi
Page 123 and 124: improvement for low idle core frequ
Page 125 and 126: 6.1.5 Direct Performance Effects Si
Page 127 and 128: of SPEC CPU2000 workloads, almost n
Page 129 and 130: adjusting a hysteresis timer. The t
Page 131 and 132: increase/decrease time. Since the i
Page 133 and 134: In order to reduce p-state performa
Page 135 and 136: performance loss and power consumpt
Page 137 and 138: eactive scheme used in Windows Vist
Page 139 and 140: Watts Watts Watts Watts Watts 150 1
Page 141 and 142: 7.2 Commercial DVFS Algorithm Exist
Page 143: of idle-active transitions in the c
Page 147 and 148: instructions. In APCI[Ac07] termino
Page 149 and 150: confidence level will drop below a
Page 151 and 152: First, prediction accuracy is consi
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Page 155 and 156: which corresponds to the DVFS sched
Page 157 and 158: Table 7.6: SYSmark 2007 Power and P
Page 159 and 160: In this case the predictor achieves
Page 161 and 162: 2007 power consumption contains man
Page 163 and 164: Chapter 8 Related Research This sec
Page 165 and 166: 8.2 System-Level Power Characteriza
Page 167 and 168: prediction scheme in this dissertat
Page 169 and 170: Chapter 9 Conclusions and Future Wo
Page 171 and 172: the duration of power and performan
Page 173 and 174: execution, portions of pipelines or
Page 175 and 176: [BiJo06-1] W. L. Bircher and L. Joh
Page 177 and 178: the 2005 ACM SIGMETRICS Internation
Page 179 and 180: [HaKe07] H. Hanson, S.W. Keckler, K
Page 181 and 182: [JoMa01] R. Joseph and M. Martonosi
Page 183 and 184: [LiBr05] Y. Li, D. Brooks, Z. Hu, a
Page 185 and 186: [Os06] Open Source Development Lab,
Page 187 and 188: [WaCh08] X. Wang and M. Chen. Clust
Page 189 and 190: [PiSh01] P. Pillai and K. G. Shin.
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Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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