Copyright by William Lloyd Bircher 2010 - The Laboratory for ...
Copyright by William Lloyd Bircher 2010 - The Laboratory for ...
Copyright by William Lloyd Bircher 2010 - The Laboratory for ...
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<strong>The</strong> difference between C0-Idle and C0-Max is determined <strong>by</strong> the amount of power spent<br />
in switching transistors, which would otherwise be clock-gated, combined with worst-<br />
case switching due to data dependencies. C0-Max can be thought of as a pathological<br />
workload in which all functional units on all cores are 100 percent utilized and the<br />
datapath constantly switches between 0 and 1. All active phases of real workloads exist<br />
somewhere between these two curves. High-IPC compute-bound workloads are closer to<br />
C0-Max while low-IPC memory-bound workloads are near C0-Idle.<br />
3.4.5 Power Management-Aware Model<br />
<strong>The</strong> model improves on existing on-line models [Be00] [BiJo06-1] [IsMa03] <strong>by</strong><br />
accounting <strong>for</strong> power management and temperature effects. Like existing models it<br />
contains a workload dependent portion that is dominated <strong>by</strong> the number of instructions<br />
completed per second. In this case the number of fetched operations per second is used<br />
in lieu of instructions completed. <strong>The</strong> fetched µops metric is preferred as it also accounts<br />
<strong>for</strong> speculative execution. In addition to fetched µops, a retired floating point µops<br />
metric is also included. This accounts <strong>for</strong> the power difference between integer and<br />
floating point ops in the AMD processor. Unlike the Pentium 4 processor which exhibits<br />
little difference in power consumption between integer and floating point applications,<br />
the AMD processor exhibits much higher power consumption <strong>for</strong> high-throughput<br />
floating point applications. A further distinction of this model is that it contains a<br />
temperature dependent portion. Using workloads with constant utilization, processor<br />
temperature and voltage are varied to observe the impact on static leakage power.<br />
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