Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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Level (Watts,Util%) Most Recent Phase 1 2 3 Time 4 LengthTn-1 LengthTn GPHR Size = 2 Detected Pattern Length1, Level1 LengthTn-1, LevelTn-1 LengthTn-1, LevelTn-1 LengthTn-1, LevelTn-1 132 Length2, Level2 LengthTn, LevelTn LengthTn, LevelTn LengthTn, LevelTn GPHR Size = 2 Predicted Phase Length4, Level4 LengthTn+2, LevelTn+2 LengthTn+2, LevelTn+2 LengthTn+2, LevelTn+2 Figure 7.5: Periodic Power Phase Predictor TimeStamp 4 Tn+2 Tn+2 Tn+2 Confidence 100% Conf% Conf% Conf% Valid Pending True True For Windows operating systems, the boot strap processor remains idle for periods of 16 milliseconds interrupted by active periods lasting about 100 microseconds. The predictor tracks the duration of the idle and active phases in the length and level fields. As a pattern of active and idle period repeats the predictor updates the quality of the prediction using the confidence field. When a pattern is first identified, it is copied to the GPHT and assigned a confidence level of 100%. The correctness of the prediction is assessed by comparing the predicted time and level of the next transition (timestamp field) to the actual transition. If a misprediction in duration or level is found, the confidence is reduced by a tunable percentage. If multiple mispredictions occur, the T/F T/F T/F T/F T/F T/F GPHT Size
confidence level will drop below a confidence limit. The net effect of these parameters is that a prediction will be invalidated after three consecutive mispredictions. The valid and pending fields are used to determine which predictor entries can be used for predictor matches and which have outstanding predictions respectively. Multiple predictions can be outstanding. If conflicting prediction exist at an evaluation point, the higher confidence prediction is used. For equal confidence predictions, the lower index prediction is used. Additional details for each predictor field are provided in Table 7.2. An example of the PPPP tracking and predicting core utilization level is given in Figure 7.6. Utilization Utilization 80% 20% 80% 20% 1ms 4ms Time (ms) 2ms 2ms Time (ms) Figure 7.6: Example of Program Phase Mapping to Predictor 133 Pattern 1ms, 20% 2ms, 20% 4ms, 80% Pattern 2ms, 80% Pred. Phase 4ms, 80% Pred. Phase 2ms, 80% Time Stamp 1ms Time Stamp 2ms
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Power (Watts) 30 25 20 15 10 5 0 Co
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workloads become more memory-bound,
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At the other extreme, the productiv
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
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average access time to the distant
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Watts Figure 5.6 Disk Power Model (
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Page 175 and 176: [BiJo06-1] W. L. Bircher and L. Joh
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Page 181 and 182: [JoMa01] R. Joseph and M. Martonosi
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Page 185 and 186: [Os06] Open Source Development Lab,
Page 187 and 188: [WaCh08] X. Wang and M. Chen. Clust
Page 189 and 190: [PiSh01] P. Pillai and K. G. Shin.
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