Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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to aliasing were introduced that affected average power results. Much greater variation can be found within each workload. 4.1.2 SPEC CPU 2000/2006 CPU and Memory Power Comparison Compared to desktop and mobile systems servers have a different power consumption composition across subsystems. Due to the presence of large memory subsystems, DIMM power is a much larger component. Also, larger working sets such as those found in SPEC CPU2006 compared to SPEC CPU2000 shift power consumption from the cores to the DIMMs. Consider CPU2000 in Figure 4.2 and CPU2006 in Figure 4.3. Due to comparatively small working sets, CPU2000 workloads are able to achieve higher core power levels. The reason is that, since the working set fits completely within the on-chip caches, the processor is able to maintain high levels of utilization. This is made more evident by the power increases seen as the number of simultaneous threads is increased from one to four. Since there is less performance dependence on the memory interface, utilization and power continue to increase as threads are added. The result is different for SPEC CPU2006. Due to the increased working set size of this benchmark, the memory subsystem limits performance. Therefore, core power is reduced significantly for the four-thread case. Differences for the single-thread case are much less, due to a reduced dependency on the memory subsystem. The shift in utilization from the core to the memory subsystem can be seen clearly in Figure 4.4. For the most compute-bound workloads, core power is five times larger than DIMM power. However, as the 46
workloads become more memory-bound, the power levels converge to the point where DIMM power slightly exceeds core power. Watts Watts 60 50 40 30 20 10 0 60 50 40 30 20 10 0 53 53 53 50 49 49 49 48 48 48 48 48 47 46 46 46 46 45 45 45 45 43 42 42 40 39 38 20 20 20 20 20 19 19 19 19 19 19 19 19 19 19 19 19 19 18 18 18 18 18 18 17 17 17 Figure 4.2 CPU2000 Average Core Power - 1 Thread vs. 4 Thread Figure 4.3 CPU2006 Average Core Power - 1 Thread vs. 4 Thread 47 SPEC2000-1x SPEC2000-4x Desktop 33 29 crafty perlbmk eon gzip parser gap mesa galgel gcc vortex mgrid bzip2 sixtrack vpr Average apsi wupwise facerec ammp fma3d twolf lucas equake applu art swim mcf 3D VideoCreation Elearning Productivity 50 49 49 48 48 48 47 46 46 46 45 45 43 42 42 42 41 40 40 40 39 39 38 37 37 35 35 35 34 34 33 29 20 20 19 19 19 19 19 19 19 19 19 18 18 18 18 18 18 17 17 17 17 17 17 16 16 16 16 16 16 16 gamess h264ref hmmer calculix namd povray gromacs perlbench gobmk dealII sjeng tonto xalancbmk cactusadm bzip2 Average astar gcc sphinx3 wrf bwaves zeusmp leslie3d omnetpp gemsfdtd soplex mcf libquantum milc lbm 3D VideoCreation Elearning Productivity 19 14 SPEC2006-1x SPEC2006-4x Desktop 19 14
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
Page 11 and 12: 5.3.6 Memory ......................
Page 13 and 14: List of Tables Table 1.1 Windows Vi
Page 15 and 16: List of Figures Figure 1.1 CPU Core
Page 17 and 18: Chapter 1 Introduction Computing sy
Page 19 and 20: increases the overhead of adaptatio
Page 21 and 22: suboptimal from a power and perform
Page 23 and 24: Active Core Activity Idle except fo
Page 25 and 26: 4. Design a predictive power manage
Page 27 and 28: 1.7 Organization This dissertation
Page 29 and 30: Chapter 2 Methodology The developme
Page 31 and 32: 2.1.2 Subsystem-Level Power in a Se
Page 33 and 34: The main components are subsystem p
Page 35 and 36: Table 2.4 Laptop System Description
Page 37 and 38: 2.3 Performance Counter Sampling To
Page 39 and 40: instruction streams that exercise a
Page 41 and 42: the power trace to the PMC trace co
Page 43 and 44: The first bar in Figure 3.1 “Fetc
Page 45 and 46: Table 3.4 Instruction Linear Regres
Page 47 and 48: long time to complete, more aggress
Page 49 and 50: power adaptations as c-states. Thes
Page 51 and 52: Core Power (Watts) 60 50 40 30 20 1
Page 53 and 54: The difference between C0-Idle and
Page 55 and 56: case error is 3.3%. Alternatively s
Page 57 and 58: 3. Based on basic domain knowledge,
Page 59 and 60: 3.6 Summary This section describes
Page 61: Power (Watts) 30 25 20 15 10 5 0 Co
Page 65 and 66: At the other extreme, the productiv
Page 67 and 68: processor. In both platforms the to
Page 69 and 70: Table 4.1 Subsystem Power Standard
Page 71 and 72: the case of I/O, the observed workl
Page 73 and 74: average distribution. The apparent
Page 75 and 76: Table 4.4 Workload Phase Classifica
Page 77 and 78: Frequency 1 10 100 1000 PhaseLength
Page 79 and 80: power management, it is shown that
Page 81 and 82: power measurement hardware for mult
Page 83 and 84: memory. Since the number of main me
Page 85 and 86: TLB Misses - Loads/stores that miss
Page 87 and 88: The form of the subsystem power mod
Page 89 and 90: 5.2.2 Memory This section considers
Page 91 and 92: prefetch traffic does increase afte
Page 93 and 94: average access time to the distant
Page 95 and 96: Watts Figure 5.6 Disk Power Model (
Page 97 and 98: exhibits little variation in power
Page 99 and 100: The memory model averaged about 9%
Page 101 and 102: efficiency rather than performance.
Page 103 and 104: through the application GUI. The nu
Page 105 and 106: 1 data cache access rate dominates
Page 107 and 108: periods of disconnect, cache snoop
Page 109 and 110: 5.3.4 CPU To test the extensibility
Page 111 and 112: Despite this, high accuracy of less
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Light activity yields higher precha
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5.3.8 Chipset The Chipset power mod
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applied to the GPU core logic, larg
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Chapter 6 Performance Effects of Dy
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can be considered as predictors whi
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improvement for low idle core frequ
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6.1.5 Direct Performance Effects Si
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of SPEC CPU2000 workloads, almost n
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adjusting a hysteresis timer. The t
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increase/decrease time. Since the i
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In order to reduce p-state performa
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performance loss and power consumpt
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eactive scheme used in Windows Vist
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Watts Watts Watts Watts Watts 150 1
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7.2 Commercial DVFS Algorithm Exist
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of idle-active transitions in the c
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workload/operating systems adds and
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instructions. In APCI[Ac07] termino
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confidence level will drop below a
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First, prediction accuracy is consi
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coverage of 43% and accuracy over 9
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which corresponds to the DVFS sched
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Table 7.6: SYSmark 2007 Power and P
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In this case the predictor achieves
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2007 power consumption contains man
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
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[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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