Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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frees the main processor to service other subsystems in an uninterrupted manner. However, since the buffering is finite, the main processor must service and empty the buffer with the deadline or connectivity may be lost. To reduce energy consumption, several researchers [LuCh00] [KrLe00] [OkIs99] [PeBu00] [ShCh99] [PiSh01] [PoLa01] propose operating the processor at the minimum voltage and frequency that satisfies the computation deadlines as indicated by the kernel or application software. The limitation of this approach is that the deadline must be articulated in the kernel or application software. Other approaches infer deadlines through measurement and/or classification [GoCh95] [PeBu98] [WeWe94] [FlRe01] [LoSm01]. Measurement-based feedback can also be done using not-traditional metrics. Shye [ShSc08] [ShOz08] shows that user satisfaction can be correlated to performance monitoring counters and biometric sensors. Using these metrics, processor performance can be adjusted to the minimum level that satisfies the user. 152
Chapter 9 Conclusions and Future Work 9.1 Conclusions The widespread application of dynamic power management has provided the opportunity for computing systems to attain high performance and energy efficiency across a wide range of workloads. Practically, systems do not operate optimally due to the lack of effective, power management, control schemes. This is largely due to a lack of run-time power accounting and the use of reactive power management on workloads with widely varying performance and power characteristics. The objective of this dissertation is to improve the effectiveness of dynamic power management by addressing these limitations. This is achieved in the following contributions: 1) Fine-Grain Accounting of Complete System Power Consumption Using a small set of widely available performance events including IPC, cache misses and interrupts, power models are developed by measuring power consumption on actual systems. These linear and polynomial models are created using regression techniques that iteratively adjust coefficients to minimize model error. This novel approach improves upon existing research by finding that complex structures such as processors and chipsets can be accurately represented by tracking their dominant performance events. Unlike existing research that primarily relies on retired instruction or 153
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Power (Watts) 30 25 20 15 10 5 0 Co
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workloads become more memory-bound,
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At the other extreme, the productiv
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
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average access time to the distant
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Watts Figure 5.6 Disk Power Model (
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exhibits little variation in power
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The memory model averaged about 9%
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efficiency rather than performance.
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through the application GUI. The nu
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1 data cache access rate dominates
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periods of disconnect, cache snoop
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5.3.4 CPU To test the extensibility
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Despite this, high accuracy of less
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Light activity yields higher precha
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5.3.8 Chipset The Chipset power mod
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Page 187 and 188: [WaCh08] X. Wang and M. Chen. Clust
Page 189 and 190: [PiSh01] P. Pillai and K. G. Shin.
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