Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

as CPU-gcc and memory-SPECjbb have a large variety of power levels. In contrast disk-
art and chipset-mcf have as much as 300X less variation.
Table 4.2 Coefficient of Variation
CPU Chipset Memory I/O Disk
idle 8.86×10 -3 4.61×10 -3 1.17×10 -3 3.86×10 -3 1.25×10 -3
gcc 5.16×10 -2 1.13×10 -2 6.90×10 -2 4.05×10 -3 2.44×10 -3
mcf 3.37×10 -2 8.53×10 -3 3.60×10 -2 3.81×10 -3 1.50×10 -3
vortex 6.99×10 -3 4.12×10 -3 2.06×10 -2 3.11×10 -3 7.82×10 -4
art 2.47×10 -3 3.66×10 -3 5.31×10 -3 3.12×10 -3 2.51×10 -4
lucas 1.21×10 -2 6.34×10 -3 5.73×10 -3 3.09×10 -3 3.25×10 -4
mesa 6.05×10 -3 3.49×10 -3 8.81×10 -3 3.86×10 -3 3.85×10 -4
mgrid 3.58×10 -3 2.46×10 -3 3.36×10 -3 3.06×10 -3 2.37×10 -4
wupwise 1.56×10 -2 6.96×10 -3 9.45×10 -3 3.12×10 -3 4.95×10 -4
DBT-2 1.70×10 -1 6.73×10 -3 2.37×10 -2 4.35×10 -3 1.61×10 -3
SPECjbb 2.34×10 -1 1.75×10 -2 7.61×10 -2 1.70×10 -3 3.34×10 -3
The cause for this difference can be attributed to the presence or lack of power
management in the various subsystems. The most variable subsystem, the CPU, makes
use of explicit clock gating through the instruction set. Whenever the operating system is
unable to find a schedulable process, it issues the “halt” instruction. This puts the
processor in a low power mode in which the clock signal is gated off in many parts of the
chip. This mode reduces power consumption in the processor to less than 25% of typical.
Since the memory subsystem does not make use of significant power management
modes, its variation is due only to varying levels of utilization. Since these workloads
exhibit large variations in memory utilization, this has a significant impact.
In contrast, the chipset and I/O subsystems have little variation in utilization. Since these
subsystems also do not make use of power saving modes, their total variation is low. In
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