Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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AverageError = NumSamples ∑ = Modeled − Measured i 1 i NumSamples 82 i Measured i × 100% The I/O and disk models performed well under all workloads. The low error rates are partly due to low power variation / high idle power consumption. The CPU and memory subsystems had larger errors, but also larger workload variation. The worst case errors for CPU occurred in the memory-bound workload: mcf. Due to a high CPI (cycles/instruction) of greater than ten cycles, the fetch-based power model consistently underestimates CPU power. This is because under mcf the processor only fetches one instruction every 10 cycles even though it is continuously searching for (and not finding) ready instructions in the instruction window. For mcf this speculative behavior has a high power cost that is equivalent to executing an additional 1-2 instructions/cycle. Table 5.1 Integer Average Model Error Workload CPU Chipset Memory I/O Disk Idle 1.74% 0.586% 3.80% 0.356% 0.172% Gcc 4.23% 10.9% 10.7% 0.411% 0.201% Mcf 12.3% 7.7% 2.2% 0.332% 0.154% Vortex 6.53% 13.0% 15.6% 0.295% 0.332% DBT-2 9.67% 0.561% 2.17% 5.62% 0.176% SPECjbb 9.00% 7.45% 6.14% 0.393% 0.144% DiskLoad 5.93% 3.06% 2.93% 0.706% 0.161% Integer Average 7.06 6.18% 6.22% 1.16% 0.191% All Workload Average ±3.50% 6.67 % ±3.42% ±4.92% 5.97% ±4.23% ±5.12% 8.80% ±5.54% ±1.97% 0.824% ±1.52% ±0.065% 0.390% ±0.492% (5.6)
The memory model averaged about 9% error across all workloads. Surprisingly the memory model fared better under integer workloads. The error rate for floating point workloads tended to be highest for workloads with the highest sustained power consumption. For these cases the model tends to underestimate power. Since the rate of bus transactions is similar for high and low error rate workloads it is suspected that the cause of underestimation is the access pattern. In particular the model does not account for differences in the power for read versus write access. Also, the number of active banks within the DRAM is not directly accounted for. Accounting for the mix of reads versus writes would be a simple addition to the model. However, accounting for active banks will likely require some form of locality metric. Idle power error is low for all cases indicating a good match for the DC term in the models. Chipset error is high considering the small amount of variation. This is due to the limitation of the constant model assumed for chipset power. Table 5.2 Floating Point Average Model Error Workload CPU Chipset Memory I/O Disk Art 9.65% 5.87% 8.92% 0.240% 1.90% Lucas 7.69% 1.46% 17.5 % 0.245% 0.31% Mesa 5.59% 11.3% 8.31% 0.334% 0.17% mgrid 0.360% 4.51% 11.4% 0.365% 0.55% wupwise 7.34% 5.21% 15.9% 0.588% 0.42% FP Average 6.13% 5.67% 12.41% 0.354% 0.67% All Workload Average ±3.53% 6.67 % ±3.42% ±3.57% 5.97% ±4.23% 83 ±4.13% 8.80% ±5.54% ±0.142% 0.824% ±1.52% ±0.70% 0.39% ±0.49%
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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Page 67 and 68: processor. In both platforms the to
Page 69 and 70: Table 4.1 Subsystem Power Standard
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Page 109 and 110: 5.3.4 CPU To test the extensibility
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Page 113 and 114: Light activity yields higher precha
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Page 119 and 120: Chapter 6 Performance Effects of Dy
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confidence level will drop below a
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First, prediction accuracy is consi
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coverage of 43% and accuracy over 9
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which corresponds to the DVFS sched
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Table 7.6: SYSmark 2007 Power and P
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In this case the predictor achieves
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2007 power consumption contains man
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
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[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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