Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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ead/write events. However, in practice read/write accesses are reasonable predictors. Over the long term (thousands of accesses) the number of precharge events should be related to the number of access events. The resultant model is given in Equation 5.3. A trace of the model applied to the mcf workload is shown in Figure 5.5. This workload cannot be modeled using cache misses. The model yields an average error rate of 2.2%. 5.2.3 Disk NumCPUs i= 1 2 BusTransactions i −4 BusTransactions i ∑ 29. 2− × 50. 1⋅10 + MCycle MCycle 76 × 813⋅10 The modeling of disk power at the level of the microprocessor presents two major challenges: large distance from CPU to disk and little variation in disk power consumption. Of all the subsystems considered in this study, the disk subsystem is at the greatest time and distance from the microprocessor. Watts 50 40 30 20 10 0 Measured Modeled Error 0 500 1000 Seconds 1500 Figure 5.5 Memory Power Model (Memory Bus Transactions)- mcf Therefore, there are challenges in getting timely information from the processor’s perspective. The various hardware and software structures that are intended to reduce the −8 100% 50% 0% -50% Error (%) -100% (5.3)
average access time to the distant disk by the processor make power modeling difficult. The primary structures are: microprocessor cache, operating system disk cache, I/O queues and I/O and disk caches. The structures offer the benefit of decoupling high- speed processor events from the low-speed disk events. Since the power modeling techniques rely on the close relationship between the subsystems, this is a problem. This is evidenced in the poor performance of the first attempts. Initially, we considered two events: DMA accesses and uncacheable accesses. Since the majority of disk transfers are handled through DMA by the disk controller, this appeared to be a strong predictor. The number of uncacheable accesses by the processor was also considered. Unlike the majority of application memory, memory mapped I/O (I/O address mapped to system address space) is not typically cached. Generally, I/O devices use memory mapped I/O for configuration and handshaking. Therefore, it should be possible to detect accesses to the I/O devices through uncacheable accesses. In practice neither of these metrics fully account for fine-grain power behavior. Since such little variation exists in the disk power consumption it is critical to accurately capture the variation that does exist. In this case the lack of variation is due to a lack of power management features. The addition of power management magnifies the variation present in the workload. Accounting for and modeling the small variation in the absence of power management suggests an accurate model can be constructed with power management. To address this limitation the manner in which DMA transactions are performed is noted. Coarsely stated, DMA transactions are initiated by the processor by first configuring the 77
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
Page 41 and 42: the power trace to the PMC trace co
Page 43 and 44: The first bar in Figure 3.1 “Fetc
Page 45 and 46: Table 3.4 Instruction Linear Regres
Page 47 and 48: long time to complete, more aggress
Page 49 and 50: power adaptations as c-states. Thes
Page 51 and 52: Core Power (Watts) 60 50 40 30 20 1
Page 53 and 54: The difference between C0-Idle and
Page 55 and 56: case error is 3.3%. Alternatively s
Page 57 and 58: 3. Based on basic domain knowledge,
Page 59 and 60: 3.6 Summary This section describes
Page 61 and 62: Power (Watts) 30 25 20 15 10 5 0 Co
Page 63 and 64: workloads become more memory-bound,
Page 65 and 66: At the other extreme, the productiv
Page 67 and 68: processor. In both platforms the to
Page 69 and 70: Table 4.1 Subsystem Power Standard
Page 71 and 72: the case of I/O, the observed workl
Page 73 and 74: average distribution. The apparent
Page 75 and 76: Table 4.4 Workload Phase Classifica
Page 77 and 78: Frequency 1 10 100 1000 PhaseLength
Page 79 and 80: power management, it is shown that
Page 81 and 82: power measurement hardware for mult
Page 83 and 84: memory. Since the number of main me
Page 85 and 86: TLB Misses - Loads/stores that miss
Page 87 and 88: The form of the subsystem power mod
Page 89 and 90: 5.2.2 Memory This section considers
Page 91: prefetch traffic does increase afte
Page 95 and 96: Watts Figure 5.6 Disk Power Model (
Page 97 and 98: exhibits little variation in power
Page 99 and 100: The memory model averaged about 9%
Page 101 and 102: efficiency rather than performance.
Page 103 and 104: through the application GUI. The nu
Page 105 and 106: 1 data cache access rate dominates
Page 107 and 108: periods of disconnect, cache snoop
Page 109 and 110: 5.3.4 CPU To test the extensibility
Page 111 and 112: Despite this, high accuracy of less
Page 113 and 114: Light activity yields higher precha
Page 115 and 116: 5.3.8 Chipset The Chipset power mod
Page 117 and 118: applied to the GPU core logic, larg
Page 119 and 120: Chapter 6 Performance Effects of Dy
Page 121 and 122: can be considered as predictors whi
Page 123 and 124: improvement for low idle core frequ
Page 125 and 126: 6.1.5 Direct Performance Effects Si
Page 127 and 128: of SPEC CPU2000 workloads, almost n
Page 129 and 130: adjusting a hysteresis timer. The t
Page 131 and 132: increase/decrease time. Since the i
Page 133 and 134: In order to reduce p-state performa
Page 135 and 136: performance loss and power consumpt
Page 137 and 138: eactive scheme used in Windows Vist
Page 139 and 140: Watts Watts Watts Watts Watts 150 1
Page 141 and 142: 7.2 Commercial DVFS Algorithm Exist
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of idle-active transitions in the c
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workload/operating systems adds and
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instructions. In APCI[Ac07] termino
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confidence level will drop below a
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First, prediction accuracy is consi
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coverage of 43% and accuracy over 9
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which corresponds to the DVFS sched
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Table 7.6: SYSmark 2007 Power and P
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In this case the predictor achieves
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2007 power consumption contains man
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
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[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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