Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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performance demand, reactive power management increases performance capacity sometime after the phase transition. During the time between the change in demand and capacity, performance may be less than optimal. Similarly, power consumption is suboptimal on transitions from high to low demand. The amount of performance loss is proportional to the number of phase changes in the workload and the lag between demand and capacity. For increasing performance in power-limited situations, reactions must be fast to prevent overshooting the power limit or missing opportunities to increase performance. Identifying when to adapt is complicated by the presence of multiple cores sharing power resources. Consider Figure 7.1. Core-level power consumption is shown for a system with multiple simultaneous threads. The program threads are fixed to the cores with thread N on core N, thread N-1 on core N-1, etc. Since power monitoring is typically provided at the system-level [Po10], existing power control techniques use the erratic fluctuations in the total power for predicting future behavior. This is unfortunate since in this example, the individual threads have a periodic, easily discernable pattern, while the pattern in the aggregate power is less discernable. If power phases can be tracked at the core-level, accurate dynamic power management schemes can be devised. To improve the effectiveness of power management the use of predictive, core-level power management is proposed. Rather than reacting to changes in performance demand, past activity patterns are used to predict future transitions. Rather than using aggregate power information, activity and power measured at the core-level is used. 122
Watts Watts Watts Watts Watts 150 100 50 0 50 0 50 0 50 0 50 0 Total Power = ∑CorePower N N=0 to 3 0 50 100 150 200 Seconds Phase Misalignment CorePower 0 CorePower 1 Core Power 2 CorePower 3 0 50 100 Seconds 150 200 Figure 7.1: Thread and Aggregate Power Patterns To analyze the effectiveness of the predictor the SYSmark 2007 benchmark is used. It contains numerous, desktop/personal computing applications such as Word, Excel, PowerPoint, Photoshop, Illustrator, etc. The benchmark is structured to have a high degree of program phase transitions, including extensive use of processor idle states (c- states) and performance states (p-states) [Ac07]. Rather than being strictly dominated by the characteristics of the workload itself, SYSmark 2007 accounts for the impact of periodic, operating system scheduling and I/O events. Using this observation, we 123
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Power (Watts) 30 25 20 15 10 5 0 Co
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workloads become more memory-bound,
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At the other extreme, the productiv
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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Page 175 and 176: [BiJo06-1] W. L. Bircher and L. Joh
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Page 181 and 182: [JoMa01] R. Joseph and M. Martonosi
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Page 185 and 186: [Os06] Open Source Development Lab,
Page 187 and 188: [WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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