Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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Watts 5 4 3 2 1 0 Figure 5.7 GPU Power Model (Non-Gated Clocks) – 3DMark06-HDR1 5.3.6 Memory clock gating Memory or DRAM power consumption is one of the more variable subsystems. Similar to the CPU, the application of various power management features yields a wide range of power consumption. For example consider the standard deviation of power consumption in SPECjbb of 1.096W compared to average its average of 1.71W. This variation is caused by the three modes of operation: self-refresh, precharge power down and active. Self-refresh represents the lowest power state in which DRAM contents are maintained by on-chip refresh logic. This mode has a high entry/exit latency and is only entered when the system is expected to be idle for a long period. The memory controller selects this mode as part of its hardware-controlled C1e idle [Bk09] state. Since this state is entered in conjunction with the hypertransport link disconnect, the power savings can be represented using the LinkActive% metric. Pre-charge power down is a higher-power, lower-latency alternative which provides power savings for short idle phases. This allows pre-charge power savings to be considered with normal DRAM activity power. 96 Measured Modeled Error 0 20 40 60 80 Seconds 100% 50% 0% -50% Error(%) -100%
Light activity yields higher precharge residency. DRAM activity is estimated using the DCTAccess metric. The sum of all DCT accesses on both channels (hit, miss and conflict) correlates positively to active DRAM power and negatively to precharge power savings. In most workloads this approach gave error of less than 10%. The two outliers were the CPU subtests of 3DMark06. Due to many of the memory transactions being spaced at intervals just slightly shorter than the precharge power down entry time, the model underestimates power by a larger margin. Higher accuracy would require a direct measurement of pre-charge power down residency or temporal locality of memory transactions. An example of model versus measured Memory power for SYSmark 2007- 3D is provided in Figure 5.8. The modeled power as a function of the DRAM channel access rate (DCTAccess/sec) and Hypertransport activity percentage (LinkActive%) is given in Equation 5.8. Additional details for the equation components, DCTAccess/sec and LinkActive percent are given in section 5.3.3. Watts 3 2 DIMM Power = 4x10 -8 x DCTAccess/sec + 0.7434 x LinkActive% + 0.24 Measured Modeled Error (5.8) 100% 1 0 4 cores accessing DRAM 1 core accessing DRAM -50% -100% 0 100 200 300 400 Seconds 500 600 700 Figure 5.8 DRAM Power Model (∑DCT Access, LinkActive) – SYSmark 2007-3D 97 50% 0% Error(%)
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Page 69 and 70: Table 4.1 Subsystem Power Standard
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Page 109 and 110: 5.3.4 CPU To test the extensibility
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Page 115 and 116: 5.3.8 Chipset The Chipset power mod
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Page 119 and 120: Chapter 6 Performance Effects of Dy
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Page 157 and 158: Table 7.6: SYSmark 2007 Power and P
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
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[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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