Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

One of the common enhancements is the use of write-combing memory. In write-
combining, the processor or I/O chip in this case combines several adjacent memory
transactions into a single transaction further removing the one-to-one mapping of I/O
traffic to DMA accesses on the processor memory bus. As a result, interrupt events are
better predictors of I/O power consumption. DMA events failed to capture the fine-grain
power variations. DMA events tended to have few rapid changes, almost as if the DMA
events had a low-pass filter applied to them. The details of the model can be seen in
Equation 5.5. Accounting for the large DC offset increases error significantly to 32%.
Another consideration with the model is the I/O configuration used. The model has a
significant idle power which is related to the presence to two I/O chips capable of
providing six 133MHz PCI-X buses. While typical in servers, this is not common for
smaller scale desktop/mobile systems that usually contain 2-3 I/O buses and a single I/O
chip. Further, the server only utilizes a small number of the I/O buses present. It is
expected that with a heavily populated, system with fewer I/O buses, the DC term would
become less prominent. This assumes a reasonable amount of power management within
the installed I/O devices.
NumCPUs
∑
i=
5.2.5 Chipset
1
2
Interrupt i
6 Interrupt i
32. 7 +
× 108 ⋅10
−
× 1.
12 ⋅10
Cycle
Cycle
The chipset power model is the simplest of all subsystems since a constant is all that is
required for accuracy. There are two reasons for this. First, the chipset subsystem
80
9
(5.5)