Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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3.4.5 Power Management-Aware Model ............................................................. 37 3.5 Methodology for Power Modeling ..................................................................... 40 3.6 Summary ............................................................................................................ 43 Chapter 4 System-Level Power Analysis ......................................................................44 4.1 Average Power ................................................................................................... 44 4.1.1 Server Platform - SPEC CPU, SPECjbb and DBT-2 .................................. 44 4.1.2 SPEC CPU 2000/2006 CPU and Memory Power Comparison .................. 46 4.1.3 Desktop Platform – SYSmark 2007 ............................................................ 48 4.1.4 Desktop Platform - SPEC CPU, 3DMark and SYSmark ............................ 49 4.2 Power Consumption Variation ........................................................................... 53 4.2.1 Server Platform ........................................................................................... 53 4.2.2 Desktop Platform ........................................................................................ 59 4.3 Summary ............................................................................................................ 62 Chapter 5 Modeling System-Level Power using Trickle-Down Events .....................64 5.1 Processor Events Propagate to Rest of System .................................................. 64 5.2 Complete-System Server Power Model ............................................................. 67 5.2.1 CPU ............................................................................................................. 71 5.2.2 Memory ....................................................................................................... 73 5.2.3 Disk ............................................................................................................. 76 5.2.4 I/O ............................................................................................................... 79 5.2.5 Chipset ........................................................................................................ 80 5.2.6 Model Validation ........................................................................................ 81 5.3 Complete-System Desktop Power Model .......................................................... 84 5.3.1 System Description ..................................................................................... 84 5.3.2 Workloads ................................................................................................... 86 5.3.3 Performance Event Selection ...................................................................... 88 5.3.4 CPU ............................................................................................................. 93 5.3.5 GPU............................................................................................................. 94 x
5.3.6 Memory ....................................................................................................... 96 5.3.7 Memory Controller ..................................................................................... 98 5.3.8 Chipset ........................................................................................................ 99 5.3.9 Disk ............................................................................................................. 99 5.3.10 Model Validation ........................................................................................ 99 5.4 Summary .......................................................................................................... 102 Chapter 6 Performance Effects of Dynamic Power Management ...........................103 6.1 Direct and Indirect Performance Impacts......................................................... 103 6.1.1 Transition Costs ........................................................................................ 103 6.1.2 Workload Phase and Policy Costs ............................................................ 104 6.1.3 Performance Effects .................................................................................. 105 6.1.4 Indirect Performance Effects .................................................................... 107 6.1.5 Direct Performance Effects ....................................................................... 109 6.2 Reactive Power Management ........................................................................... 110 6.2.1 Power and Performance Results ............................................................... 116 6.3 Summary .......................................................................................................... 118 Chapter 7 Predictive Power Management ..................................................................120 7.1 Core-Level Activity Prediction ........................................................................ 120 7.2 Commercial DVFS Algorithm ......................................................................... 125 7.3 Workload Characterization .............................................................................. 126 7.4 Periodic Power Phase Predictor – PPPP .......................................................... 130 7.5 Predicting Core Activity Level ........................................................................ 134 7.6 Predicting Power Levels................................................................................... 143 7.7 Summary .......................................................................................................... 145 Chapter 8 Related Research ........................................................................................147 8.1 Performance Counter-Driven Power Models ........................................................ 147 8.2 System-Level Power Characterization .................................................................. 149 8.3 Predictive Power Adaptation ................................................................................. 150 xi
Page 1 and 2: Copyright by William Lloyd Bircher
Page 3 and 4: Predictive Power Management for Mul
Page 5 and 6: Acknowledgements I would like to th
Page 7 and 8: Predictive Power Management for Mul
Page 9: Table of Contents Chapter 1 Introdu
Page 13 and 14: List of Tables Table 1.1 Windows Vi
Page 15 and 16: List of Figures Figure 1.1 CPU Core
Page 17 and 18: Chapter 1 Introduction Computing sy
Page 19 and 20: increases the overhead of adaptatio
Page 21 and 22: suboptimal from a power and perform
Page 23 and 24: Active Core Activity Idle except fo
Page 25 and 26: 4. Design a predictive power manage
Page 27 and 28: 1.7 Organization This dissertation
Page 29 and 30: Chapter 2 Methodology The developme
Page 31 and 32: 2.1.2 Subsystem-Level Power in a Se
Page 33 and 34: The main components are subsystem p
Page 35 and 36: Table 2.4 Laptop System Description
Page 37 and 38: 2.3 Performance Counter Sampling To
Page 39 and 40: instruction streams that exercise a
Page 41 and 42: the power trace to the PMC trace co
Page 43 and 44: The first bar in Figure 3.1 “Fetc
Page 45 and 46: Table 3.4 Instruction Linear Regres
Page 47 and 48: long time to complete, more aggress
Page 49 and 50: power adaptations as c-states. Thes
Page 51 and 52: Core Power (Watts) 60 50 40 30 20 1
Page 53 and 54: The difference between C0-Idle and
Page 55 and 56: case error is 3.3%. Alternatively s
Page 57 and 58: 3. Based on basic domain knowledge,
Page 59 and 60: 3.6 Summary This section describes
Page 61 and 62:
Power (Watts) 30 25 20 15 10 5 0 Co
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workloads become more memory-bound,
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At the other extreme, the productiv
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
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average access time to the distant
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Watts Figure 5.6 Disk Power Model (
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exhibits little variation in power
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The memory model averaged about 9%
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efficiency rather than performance.
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through the application GUI. The nu
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1 data cache access rate dominates
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periods of disconnect, cache snoop
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5.3.4 CPU To test the extensibility
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Despite this, high accuracy of less
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Light activity yields higher precha
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5.3.8 Chipset The Chipset power mod
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applied to the GPU core logic, larg
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Chapter 6 Performance Effects of Dy
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can be considered as predictors whi
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improvement for low idle core frequ
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6.1.5 Direct Performance Effects Si
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of SPEC CPU2000 workloads, almost n
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adjusting a hysteresis timer. The t
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increase/decrease time. Since the i
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In order to reduce p-state performa
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performance loss and power consumpt
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eactive scheme used in Windows Vist
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Watts Watts Watts Watts Watts 150 1
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7.2 Commercial DVFS Algorithm Exist
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of idle-active transitions in the c
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workload/operating systems adds and
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instructions. In APCI[Ac07] termino
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confidence level will drop below a
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First, prediction accuracy is consi
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coverage of 43% and accuracy over 9
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which corresponds to the DVFS sched
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Table 7.6: SYSmark 2007 Power and P
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In this case the predictor achieves
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2007 power consumption contains man
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
Page 181 and 182:
[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
Page 185 and 186:
[Os06] Open Source Development Lab,
Page 187 and 188:
[WaCh08] X. Wang and M. Chen. Clust
Page 189 and 190:
[PiSh01] P. Pillai and K. G. Shin.
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Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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