Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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as CPU-gcc and memory-SPECjbb have a large variety of power levels. In contrast disk- art and chipset-mcf have as much as 300X less variation. Table 4.2 Coefficient of Variation CPU Chipset Memory I/O Disk idle 8.86×10 -3 4.61×10 -3 1.17×10 -3 3.86×10 -3 1.25×10 -3 gcc 5.16×10 -2 1.13×10 -2 6.90×10 -2 4.05×10 -3 2.44×10 -3 mcf 3.37×10 -2 8.53×10 -3 3.60×10 -2 3.81×10 -3 1.50×10 -3 vortex 6.99×10 -3 4.12×10 -3 2.06×10 -2 3.11×10 -3 7.82×10 -4 art 2.47×10 -3 3.66×10 -3 5.31×10 -3 3.12×10 -3 2.51×10 -4 lucas 1.21×10 -2 6.34×10 -3 5.73×10 -3 3.09×10 -3 3.25×10 -4 mesa 6.05×10 -3 3.49×10 -3 8.81×10 -3 3.86×10 -3 3.85×10 -4 mgrid 3.58×10 -3 2.46×10 -3 3.36×10 -3 3.06×10 -3 2.37×10 -4 wupwise 1.56×10 -2 6.96×10 -3 9.45×10 -3 3.12×10 -3 4.95×10 -4 DBT-2 1.70×10 -1 6.73×10 -3 2.37×10 -2 4.35×10 -3 1.61×10 -3 SPECjbb 2.34×10 -1 1.75×10 -2 7.61×10 -2 1.70×10 -3 3.34×10 -3 The cause for this difference can be attributed to the presence or lack of power management in the various subsystems. The most variable subsystem, the CPU, makes use of explicit clock gating through the instruction set. Whenever the operating system is unable to find a schedulable process, it issues the “halt” instruction. This puts the processor in a low power mode in which the clock signal is gated off in many parts of the chip. This mode reduces power consumption in the processor to less than 25% of typical. Since the memory subsystem does not make use of significant power management modes, its variation is due only to varying levels of utilization. Since these workloads exhibit large variations in memory utilization, this has a significant impact. In contrast, the chipset and I/O subsystems have little variation in utilization. Since these subsystems also do not make use of power saving modes, their total variation is low. In 54
the case of I/O, the observed workloads make little or no use of disk and network resources. For the chipset subsystem, the causes are not as clear and require further study. As mentioned in the previous section the lack of disk power management causes little variation in disk power consumption. If these subsystems are to benefit from dynamic adaptation, workloads with larger variation in utilization would be needed. In order to justify the use of CoV for identifying workloads with distinct, adaptable phases the probability distributions for extreme cases are considered. In order for a subsystem-workload pair to be a strong candidate for optimization, it must have distinct program/power phases. If a workload exhibits constant power consumption it is difficult to identify distinct phases. Further if the difference in phases is small, it may be difficult to distinguish a phase in the presence of sampling noise. Therefore, a strong candidate should have multiple distinct phases. This can be observed in the power amplitude distributions in Figure 4.7. A narrow distribution represents a constant power consumption. A wide distribution represents many levels of power consumption. Distinct power phases only exist in the wide distributions. Figure 4.7 shows the average power distribution for the various subsystems. Not surprisingly, CPUs are the dominant power users. However, unlike distributed, scientific NAS Parallel Benchmark [FeGe05-1] and mobile, productivity workloads such as PCMark and 3DMark [MaVa04], I/O and disk power are significant. While differences in average subsystem power are large at 138% for disk compared to CPU, the variations within an individual subsystem are even greater. A comparison of subsystem power 55
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
Page 19 and 20: increases the overhead of adaptatio
Page 21 and 22: suboptimal from a power and perform
Page 23 and 24: Active Core Activity Idle except fo
Page 25 and 26: 4. Design a predictive power manage
Page 27 and 28: 1.7 Organization This dissertation
Page 29 and 30: Chapter 2 Methodology The developme
Page 31 and 32: 2.1.2 Subsystem-Level Power in a Se
Page 33 and 34: The main components are subsystem p
Page 35 and 36: Table 2.4 Laptop System Description
Page 37 and 38: 2.3 Performance Counter Sampling To
Page 39 and 40: instruction streams that exercise a
Page 41 and 42: the power trace to the PMC trace co
Page 43 and 44: The first bar in Figure 3.1 “Fetc
Page 45 and 46: Table 3.4 Instruction Linear Regres
Page 47 and 48: long time to complete, more aggress
Page 49 and 50: power adaptations as c-states. Thes
Page 51 and 52: Core Power (Watts) 60 50 40 30 20 1
Page 53 and 54: The difference between C0-Idle and
Page 55 and 56: case error is 3.3%. Alternatively s
Page 57 and 58: 3. Based on basic domain knowledge,
Page 59 and 60: 3.6 Summary This section describes
Page 61 and 62: Power (Watts) 30 25 20 15 10 5 0 Co
Page 63 and 64: workloads become more memory-bound,
Page 65 and 66: At the other extreme, the productiv
Page 67 and 68: processor. In both platforms the to
Page 69: Table 4.1 Subsystem Power Standard
Page 73 and 74: average distribution. The apparent
Page 75 and 76: Table 4.4 Workload Phase Classifica
Page 77 and 78: Frequency 1 10 100 1000 PhaseLength
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Page 81 and 82: power measurement hardware for mult
Page 83 and 84: memory. Since the number of main me
Page 85 and 86: TLB Misses - Loads/stores that miss
Page 87 and 88: The form of the subsystem power mod
Page 89 and 90: 5.2.2 Memory This section considers
Page 91 and 92: prefetch traffic does increase afte
Page 93 and 94: average access time to the distant
Page 95 and 96: Watts Figure 5.6 Disk Power Model (
Page 97 and 98: exhibits little variation in power
Page 99 and 100: The memory model averaged about 9%
Page 101 and 102: efficiency rather than performance.
Page 103 and 104: through the application GUI. The nu
Page 105 and 106: 1 data cache access rate dominates
Page 107 and 108: periods of disconnect, cache snoop
Page 109 and 110: 5.3.4 CPU To test the extensibility
Page 111 and 112: Despite this, high accuracy of less
Page 113 and 114: Light activity yields higher precha
Page 115 and 116: 5.3.8 Chipset The Chipset power mod
Page 117 and 118: applied to the GPU core logic, larg
Page 119 and 120: Chapter 6 Performance Effects of Dy
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can be considered as predictors whi
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improvement for low idle core frequ
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6.1.5 Direct Performance Effects Si
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of SPEC CPU2000 workloads, almost n
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adjusting a hysteresis timer. The t
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increase/decrease time. Since the i
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In order to reduce p-state performa
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performance loss and power consumpt
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eactive scheme used in Windows Vist
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Watts Watts Watts Watts Watts 150 1
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7.2 Commercial DVFS Algorithm Exist
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of idle-active transitions in the c
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workload/operating systems adds and
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instructions. In APCI[Ac07] termino
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confidence level will drop below a
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First, prediction accuracy is consi
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coverage of 43% and accuracy over 9
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which corresponds to the DVFS sched
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Table 7.6: SYSmark 2007 Power and P
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In this case the predictor achieves
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2007 power consumption contains man
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
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[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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