Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

5.3.4 CPU
To test the extensibility of performance counter power modeling across processor
architectures, the methodology is applied to an AMD Phenom quad-core processor. Like
the Intel Pentium 4 processor used in sections 3.2 and 3.3, fetched instructions is a
dominant metric for power accounting. Differences in architecture and microarchitecture
dictate that additional metrics are needed to attain high accuracy. Two areas are
prominent: floating point instruction power and architectural power management. Unlike
the Intel server processor which exhibits nearly statistically uniform power consumption
across workloads of similar fetch rate, the AMD desktop processor consumes up to 30%
more power for workloads with large proportions of floating point instructions.
To account for the difference in floating point instruction power, the desktop processor
model employs an additional metric for retired floating point instructions. A still larger
power difference is caused by the addition of architectural power management on the
desktop processor. The older, server processor only has architectural power management
in the form of clock gating when the halt instruction is issued by the operating system.
The newer, desktop processor adds architectural, DVFS. This leads to drastic reductions
in switching and leakage power. To account for these power reductions, the desktop
model includes tracking of processor frequency, voltage and temperature. The details of
the model can be found in Section 3.4.5.
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