Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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Watts 90 80 70 60 50 40 30 20 10 0 DIMM CPU 10 17 25 18 10 9 16 16 14 21 12 22 26 29 25 25 25 25 34 34 36 29 38 32 38 33 35 34 36 39 50 49 49 48 48 48 47 46 46 46 45 45 43 42 42 42 41 40 40 40 39 39 38 37 37 35 35 35 34 34 gamess h264ref hmmer calculix namd povray gromacs perlbench gobmk dealII sjeng tonto xalancbmk cactusADM bzip2 Average astar gcc sphinx3 wrf bwaves zeusmp leslie3d omnetpp GemsFDTD soplex mcf libquantum milc lbm Figure 4.4 SPEC CPU2006 Average Core vs. DIMM Power 4.1.3 Desktop Platform – SYSmark 2007 In this section average power consumption levels across a range of workloads are considered. Two major conclusions for desktop workloads are drawn: the core is the largest power consumer and it contains the most variability across workloads. Though other subsystems, such as memory controller and DIMM, have significant variability within workloads, only the core demonstrates significant variability in average power across desktop workloads. Consider Figure 4.5: while average core power varies by as much as 57 percent, the next most variable subsystem, DIMM, varies by only 17 percent. Note, this conclusion does not hold for server systems and workloads in which much larger installations of memory modules cause greater variability in power consumption. The cause of this core power variation can be attributed to a combination of variable levels of thread-level parallelism and core-level power adaptations. In the case of 3D, the workload is able to consistently utilize multiple cores. 48
At the other extreme, the productivity workload rarely utilizes more than a single core. Since Quad-Core AMD processor power adaptations are applied at the core level, frequency reduction achieves significant power savings on the three idle cores. As a result, the productivity workload consumes much less power than the 3D workload. The remaining workloads offer intermediate levels of thread-level parallelism and therefore have intermediate levels of power consumption. Also note that this level of power reduction is due only to frequency scaling. With the addition of core-level voltage scaling, the variation/power savings is expected to increase considerably. Power(Watts) 90 80 70 60 50 40 30 20 10 0 33.1 18.7 10.9 10.5 10.3 10.1 13.9 13.8 13.7 13.8 22.1 22.2 21.1 22.0 3.7 3.7 3.7 3.6 Figure 4.5 Desktop Subsystem Power Breakdown 4.1.4 Desktop Platform - SPEC CPU, 3DMark and SYSmark To understand subsystem-level power consumption average and standard deviation results are presented. Figure 4.6 displays average power of each subsystem measured in Watts. To give an indication of the variation in power consumption Table 4.1 displays 49 14.3 29.4 3D E-Learning Productivity Video Creation CPU Memory I/O Disk Video
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
Page 13 and 14: List of Tables Table 1.1 Windows Vi
Page 15 and 16: List of Figures Figure 1.1 CPU Core
Page 17 and 18: Chapter 1 Introduction Computing sy
Page 19 and 20: increases the overhead of adaptatio
Page 21 and 22: suboptimal from a power and perform
Page 23 and 24: Active Core Activity Idle except fo
Page 25 and 26: 4. Design a predictive power manage
Page 27 and 28: 1.7 Organization This dissertation
Page 29 and 30: Chapter 2 Methodology The developme
Page 31 and 32: 2.1.2 Subsystem-Level Power in a Se
Page 33 and 34: The main components are subsystem p
Page 35 and 36: Table 2.4 Laptop System Description
Page 37 and 38: 2.3 Performance Counter Sampling To
Page 39 and 40: instruction streams that exercise a
Page 41 and 42: the power trace to the PMC trace co
Page 43 and 44: The first bar in Figure 3.1 “Fetc
Page 45 and 46: Table 3.4 Instruction Linear Regres
Page 47 and 48: long time to complete, more aggress
Page 49 and 50: power adaptations as c-states. Thes
Page 51 and 52: Core Power (Watts) 60 50 40 30 20 1
Page 53 and 54: The difference between C0-Idle and
Page 55 and 56: case error is 3.3%. Alternatively s
Page 57 and 58: 3. Based on basic domain knowledge,
Page 59 and 60: 3.6 Summary This section describes
Page 61 and 62: Power (Watts) 30 25 20 15 10 5 0 Co
Page 63: workloads become more memory-bound,
Page 67 and 68: processor. In both platforms the to
Page 69 and 70: Table 4.1 Subsystem Power Standard
Page 71 and 72: the case of I/O, the observed workl
Page 73 and 74: average distribution. The apparent
Page 75 and 76: Table 4.4 Workload Phase Classifica
Page 77 and 78: Frequency 1 10 100 1000 PhaseLength
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Page 81 and 82: power measurement hardware for mult
Page 83 and 84: memory. Since the number of main me
Page 85 and 86: TLB Misses - Loads/stores that miss
Page 87 and 88: The form of the subsystem power mod
Page 89 and 90: 5.2.2 Memory This section considers
Page 91 and 92: prefetch traffic does increase afte
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Page 95 and 96: Watts Figure 5.6 Disk Power Model (
Page 97 and 98: exhibits little variation in power
Page 99 and 100: The memory model averaged about 9%
Page 101 and 102: efficiency rather than performance.
Page 103 and 104: through the application GUI. The nu
Page 105 and 106: 1 data cache access rate dominates
Page 107 and 108: periods of disconnect, cache snoop
Page 109 and 110: 5.3.4 CPU To test the extensibility
Page 111 and 112: Despite this, high accuracy of less
Page 113 and 114: Light activity yields higher precha
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5.3.8 Chipset The Chipset power mod
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applied to the GPU core logic, larg
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Chapter 6 Performance Effects of Dy
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can be considered as predictors whi
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improvement for low idle core frequ
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6.1.5 Direct Performance Effects Si
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of SPEC CPU2000 workloads, almost n
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adjusting a hysteresis timer. The t
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increase/decrease time. Since the i
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In order to reduce p-state performa
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performance loss and power consumpt
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eactive scheme used in Windows Vist
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Watts Watts Watts Watts Watts 150 1
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7.2 Commercial DVFS Algorithm Exist
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of idle-active transitions in the c
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workload/operating systems adds and
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instructions. In APCI[Ac07] termino
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confidence level will drop below a
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First, prediction accuracy is consi
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coverage of 43% and accuracy over 9
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which corresponds to the DVFS sched
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Table 7.6: SYSmark 2007 Power and P
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In this case the predictor achieves
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2007 power consumption contains man
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
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[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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