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[FaWe07] X. Fan, W. Weber, and L. Barroso. A. Power provisioning for a warehouse-sized computer. In Proceedings of the 34th Annual International Symposium on Computer Architecture (San Diego, California, June 2007), 13-23. [FeGe05-1] X. Feng, R. Ge, and K. W. Cameron. Power and Energy Profiling of Scientific Applications on Distributed Systems. In Proceedings of the 19 th IEEE International Parallel & Distributed Processing Symposium (Denver, Colorado, April 2005), 34-50. [GaJo10] K. Genesan, J. Jo, W. L. Bircher, D. Kaseridis, Z. Yu and L. John. System-level Max Power (SYMPO) – A Systematic Approach for Escalating System- Level Power Consumption using Synthetic Benchmarks. In Proceedings of the 2010 International Conference on Parallel Architectures and Compilation Techniques (Vienna, Austria, June 2010), 19-28. [GuSi02] S. Gurumurthi, A. Sivasubramaniam, M. J. Irwin, N. Vijaykrishnan, M. Kandemir, T. Li, and L. K. John. Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach. In Proceedings of the 8th International Symposium on High-Performance Computer Architecture (Boston, Massachusetts, February 2002), 141-150. [HaKe06] H. Hanson and S. W. Keckler. Power and Performance Optimization: A Case Study with the Pentium M Processor. 7th International Austin Center for Advanced Studies (IBM) Conference (Austin, Texas, February 2006). 162
[HaKe07] H. Hanson, S.W. Keckler, K. Rajamani, S. Ghiasi, F. Rawson, and J. Rubio. Power, Performance, and Thermal Management for High-Performance Systems. In Proceedings of The Third Workshop on High-Performance, Power-Aware Computing, held in conjunction with 21st Annual International Parallel & Distributed Processing Symposium (Long Beach, California, March 2007). [HeCe06] T. Heath, A. P. Centeno, P. George, L. Ramos, Y. Jaluria, and R. Bianchini. Mercury and Freon: Temperature Emulation and Management in Server Systems. In Proceedings of the 12 th International Conference on Architectural Support for Programming Languages and Operating Systems (San Jose, California, October 2006), 106-116. [Am07] Inside Barcelona: AMD's Next Generation http://www.realworldtech.com . November 2007. [In04] Intel Corporation. IA-32 Architecture Optimization Reference Manual. 2004. [In06] Intel Software Network. Thermal Protection And Monitoring Features: A Software Perspective. www.intel.com/cd/ids/developer/asmona/eng/newsletter, February 2006. 163
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Power (Watts) 30 25 20 15 10 5 0 Co
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workloads become more memory-bound,
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At the other extreme, the productiv
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
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average access time to the distant
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Watts Figure 5.6 Disk Power Model (
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exhibits little variation in power
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The memory model averaged about 9%
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efficiency rather than performance.
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through the application GUI. The nu
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1 data cache access rate dominates
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periods of disconnect, cache snoop
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5.3.4 CPU To test the extensibility
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Despite this, high accuracy of less
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Light activity yields higher precha
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5.3.8 Chipset The Chipset power mod
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applied to the GPU core logic, larg
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Chapter 6 Performance Effects of Dy
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can be considered as predictors whi
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improvement for low idle core frequ
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6.1.5 Direct Performance Effects Si
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Page 187 and 188: [WaCh08] X. Wang and M. Chen. Clust
Page 189 and 190: [PiSh01] P. Pillai and K. G. Shin.
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