Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

List of Figures
Figure 1.1 CPU Core-Level Power Accounting.............................................................. 3
Figure 1.2 System-Level Power Accounting .................................................................. 4
Figure 1.3 Core Activity Patterns – Blu-Ray Playback .................................................. 7
Figure 1.4 Thread and Aggregate Power Patterns........................................................... 8
Figure 2.1 Current Sense Amplification PCB ............................................................... 16
Figure 2.2 Power Measurement Environment .............................................................. 17
Figure 2.3 Leakage Power Determination..................................................................... 20
Figure 3.1. Average µOps/cycle - SPEC CPU 2000 ..................................................... 27
Figure 3.2 Temperature Sensitivity of Leakage Power ................................................. 35
Figure 3.3 Power by C-state/P-state Combination ........................................................ 36
Figure 3.4 CPU Power Model – SPEC CPU 2006 Power and Average Error ............. 39
Figure 3.5 Trickle-Down Modeling Process ................................................................. 42
Figure 4.1 Average Power Consumption (Watts) ........................................................ 45
Figure 4.2 CPU2000 Average Core Power - 1 Thread vs. 4 Thread............................. 47
Figure 4.3 CPU2006 Average Core Power - 1 Thread vs. 4 Thread............................. 47
Figure 4.4 SPEC CPU2006 Average Core vs. DIMM Power ....................................... 48
Figure 4.5 Desktop Subsystem Power Breakdown ....................................................... 49
Figure 4.6 Subsystem Average Power (Watts) ............................................................. 52
Figure 4.7 Subsystem Amplitude Distributions ............................................................ 57
Figure 4.8 Core Power Phase Duration ......................................................................... 61
Figure 4.9 Core Power Phases – SYSmark 2007 .......................................................... 62
Figure 5.1. Propagation of Performance Events ........................................................... 66
Figure 5.2 Processor Power Model – gcc ...................................................................... 72
Figure 5.3 Memory Power Model (L3 Misses) – mesa ................................................. 74
Figure 5.4 Prefetch and Non-Prefetch Bus Transactions – mcf .................................... 75
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