Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

power model that was used. Compare to the server power model which averaged over
6% error using only three inputs. More importantly, this low error rate suggests that
performance counter power models are effective across multiple microprocessor
architecture generations, platforms, and manufacturers (Intel and AMD).
The chipset power model is also improved compared to the server chipset model with
average error of 3.3%. Like the server model, the desktop model contained a large
workload-independent component: although in this case it contributed less than half the
total chipset power rather than the 100% seen in the server model.
The memory and memory controller power models had the highest average error with
5.3% and 6.0% respectively. The high error is largely due to the CPU portion of the
3DMark06 workload. This workload generates memory transactions at an interval that
prevents effective utilization of precharge power down modes. Therefore, the model
tends to underestimate memory power consumption. To resolve this error, a metric of
typical memory bus idle duration or power down residency would be needed.
The GPU power model had the lowest error rate at slightly less than 1%. This illustrates
the effectiveness of the non-gated GPU clocks as a proxy for GPU power. In most
workloads the GPU power has a clear bimodal characteristic. Active regions have a
power level that is consistent. Idle regions also have a consistent power level due to the
presence of idle clock gating. It is expected that as finer grain power management is
100