Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

5.3.7 Memory Controller
Since the memory controller is responsible to entry and exit of power saving modes for
itself and memory, the memory metrics can also be used to estimate memory controller
power. Though both use link active and DCTAccesses the relative weights are different.
Memory power has a large sensitivity to the transaction rate, 4 · 10 -8 W/transaction/sec.
Compare this to the memory controller which is more than four times smaller at 9 · 10 -9
W/transaction/sec. Similarly, transaction-independent portion is much higher for the
memory controller at 1.9W compared to 0.98W for memory. This reflects the
unmanaged power consumers in the memory controller. The same 3DMark06 error
outliers exist here. An example of model versus measured Memory Controller power for
3DMark06-HDR1 is provided in Figure 5.9. The modeled power is provided below in
Equation 5.9.
Watts
3.0
2.5
2.0
1.5
Memory Controller Power =
9x10 -9 x DCTAccess/sec + 0.798 x LinkActive% + 1.05
Figure 5.9 Memory Controller Power (∑DCT Access, LinkActive) – HDR1
98
100%
50%
1.0
0.5
Measured
Modeled
Error
-50%
0.0
-100%
0 20 40
Seconds
60 80 100
0%
Error(%)
(5.9)