Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

increase/decrease time. Since the increase time is much longer than TimeCheck (300 ms
vs. 10 ms), significant performance is lost even at the minimum setting.
To reduce the impact of slow p-state transitions OS settings are selected that increase
transition rates. In a general sense, frequent p-state transitions are not recommended due
to the hardware transition costs. However, these experiments have shown that the
performance cost for slow OS-directed transitions is much greater than that due to
hardware. This can be attributed to the relatively fast hardware transitions possible on
Quad-Core AMD processors. Compared to OS transitions which occur at 10 ms
intervals, worst-case hardware transitions occur in a matter of 100’s of microseconds.
Figure 6.5 shows the effect of optimizing p-state changes to the fastest rate of once every
10 ms. The probe-sensitive equake is shown with and without “fast p-states.” This
approach yields between 2 percent and 4 percent performance improvement across the
range of useful idle core frequencies. As is shown in the next section, this also improves
power savings by reducing active-to-idle transition times.
Performance
100%
98%
96%
94%
92%
90%
Average
performance
increase 1.1%
Default
Fast P-States
88%
800 1300 1800 2300
Minimum Core Frequency (MHz)
Figure 6.5 Effect of Increasing P-state Transition Rate
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