Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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Figure 5.5 Memory Power Model (Memory Bus Transactions)- mcf .......................... 76 Figure 5.6 Disk Power Model (DMA+Interrupt) – Synthetic Disk Workload ............. 79 Figure 5.7 GPU Power Model (Non-Gated Clocks) – 3DMark06-HDR1 .................... 96 Figure 5.8 DRAM Power Model (∑DCT Access, LinkActive) – SYSmark 2007-3D . 97 Figure 5.9 Memory Controller Power (∑DCT Access, LinkActive) – HDR1 ............. 98 Figure 6.1 Direct and Indirect Performance Impact .................................................... 107 Figure 6.2 Remote and Local Probe Sensitivity .......................................................... 112 Figure 6.3 C-state vs. P-state Performance ................................................................. 113 Figure 6.4 Varying OS P-state Transition Rates ......................................................... 114 Figure 7.1: Thread and Aggregate Power Patterns ..................................................... 123 Figure 7.2: Windows Vista Reactive P-State Selection Algorithm ............................ 126 Figure 7.3: Six-Core Phenom 2 Desktop Activity Levels ........................................... 128 Figure 7.4: Utilization of Multiple Cores by SYSmark 2007 Benchmark .................. 129 Figure 7.5: Periodic Power Phase Predictor ................................................................ 132 Figure 7.6: Example of Program Phase Mapping to Predictor ................................... 133 Figure 7.7 Core-Level Phase Length Probability Distributions .................................. 140 Figure 7.8 Prediction Accuracy of Core Power for Various Predictors ...................... 144 xvi
Chapter 1 Introduction Computing systems have a wide range of design objectives. Metrics such as performance, power and cost must be carefully managed in order to meet these objectives. While some parameters are fixed at design time, others such as performance and power consumption may be dynamically adjusted at run-time. This allows a system to be optimal across a wider range of workloads and usage scenarios. This dynamic optimization, commonly known as dynamic power management, allows performance to be exchanged for power savings. The amount of savings is constrained by the system objectives. For example, systems with quality of service (QoS) requirements can allow power and performance to be reduced only as long as the service demands are met. Mobile systems powered by batteries must be optimized to deliver the highest performance/Watt in order to maximize usage time. Compute-cluster performance capacity must be modulated to match demand so that performance/cost is maximized. Adaptation within these scenarios requires accurate, run-time measurement of performance and power consumption. Run-time measurement of power and performance allow tradeoffs to be made dynamically in response to program and usage patterns. 1.1 Attributing Power in Multi-Core Systems Multi-core and multi-threaded systems present significant challenges to power measurement. While performance is readily measurable at the core and program-level, 1
Page 1 and 2: Copyright by William Lloyd Bircher
Page 3 and 4: Predictive Power Management for Mul
Page 5 and 6: Acknowledgements I would like to th
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Page 9 and 10: Table of Contents Chapter 1 Introdu
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
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average access time to the distant
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Watts Figure 5.6 Disk Power Model (
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exhibits little variation in power
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The memory model averaged about 9%
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efficiency rather than performance.
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through the application GUI. The nu
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1 data cache access rate dominates
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periods of disconnect, cache snoop
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5.3.4 CPU To test the extensibility
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Despite this, high accuracy of less
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Light activity yields higher precha
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5.3.8 Chipset The Chipset power mod
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applied to the GPU core logic, larg
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Chapter 6 Performance Effects of Dy
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can be considered as predictors whi
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improvement for low idle core frequ
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6.1.5 Direct Performance Effects Si
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of SPEC CPU2000 workloads, almost n
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adjusting a hysteresis timer. The t
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increase/decrease time. Since the i
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In order to reduce p-state performa
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performance loss and power consumpt
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eactive scheme used in Windows Vist
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Watts Watts Watts Watts Watts 150 1
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7.2 Commercial DVFS Algorithm Exist
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of idle-active transitions in the c
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workload/operating systems adds and
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instructions. In APCI[Ac07] termino
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confidence level will drop below a
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First, prediction accuracy is consi
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coverage of 43% and accuracy over 9
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which corresponds to the DVFS sched
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Table 7.6: SYSmark 2007 Power and P
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In this case the predictor achieves
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2007 power consumption contains man
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
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[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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