Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

long time to complete, more aggressive power saving techniques may be performed.
Further investigation will be required to validate this hypothesis. Since Table 3.5
supports the conclusion that high latency instructions consume less power, the models
can be improved by accounting for this behavior. One possible accounting method is to
note that most high latency instructions are composed of relatively long µop sequences
sourced by the microcode ROM. Microcode ROM events can be observed using the
trace cache metric, microrom µops. This metric counts the number of µops delivered
from the microcode ROM. The resultant models are given in Table 3.6. As expected
from the observations of power consumption of microcode ROM delivered instructions,
the model’s microcode ROM component is negative. This small correction allows the
power model to extend below 36W for workloads with high instances of complex
microcode ROM instructions.
Table 3.6 µop Linear Regression Model Comparison
Deliver, µROM Deliver, µROM, Build
α0 α1 α2 α0 α1 α2 α3
36.7 4.24 -11.8 36.7 4.24 -14.6 5.74
Avg Error 2.50% 2.55%
Coefficients
Coefficient of
Determination
3.4 Power Management Effects
0.844 0.850
While instruction and µop-based power models accurately account for power during fully
active phases, they perform poorly in the presence of dynamic power management and
temperature variation. This section characterizes the effect that power adaptations such
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