Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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Bibliography [Ac07] Advanced Configuration & Power Interface. http://www.acpi.info (November 2007). [Ag08] Agilent Technologies. 1146A 100 kHz /100A AC/DC Current Probe. http://www.agilent.com, April 2008. [An73] F. J. Anscombe. Graphs in Statistical Analysis. American Statistician, pages 17-21, February 1973. [Be00] F. Bellosa. The Benefits of Event-Driven Energy Accounting in Power- Sensitive Systems. In Proceedings of the 9th Workshop on ACM SIGOPS European Workshop: Beyond the PC: New Challenges for the Operating System (Kolding, Denmark, September 2000), 37-42. [Bk09] BIOS and Kernel Developer’s Guide for AMD Family 10h Processor. http://www.amd.com. November 2009. [BiVa05] W. L. Bircher, M. Valluri, J. Law, and L. John. Runtime identification of microprocessor energy saving opportunities. In Proceedings of the 2005 International Symposium on Low Power Electronics and Design (San Diego, California, August 2005), 275-280. 158
[BiJo06-1] W. L. Bircher and L. John. Complete System Power Estimation: A Trickle-Down Approach based on Performance Events. In IEEE International Symposium on Performance Analysis of Systems and Software (San Jose, California, April 2007), 158-168. [Bi06] W. L. Bircher. Measurement Based Power Phase Analysis of a Commercial Workload. 2 nd IEEE Workshop on Unique Chips and Systems (Austin, Texas, March 2006). [BiJo06-3] W. L. Bircher and L. John. Power Phase Availability in a Commercial Server Workload. In Proceedings of the 2006 International Symposium on Low Power Electronics and Design (Tegernsee, Germany, October 2006), 350-353. [BiJo08] W. L. Bircher and L. John. Analysis of Dynamic Power Management on Multi-Core Processors. In Proceedings of the 22 nd Annual International Conference on Supercomputing (Kos, Greece, June 2008), 327-338. [BiJo10-1] W. L. Bircher and L. John. Complete System Power Estimation using Processor Performance Events. Under Review at IEEE Transactions on Computers (October 2010). [BiJo10-2] W. L. Bircher and L. John. Predictive Power Management for Multi-Core Processors. In Workshop on Energy Efficient Design (Saint-Malo, France, June 2010), 327-338. 159
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Power (Watts) 30 25 20 15 10 5 0 Co
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workloads become more memory-bound,
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At the other extreme, the productiv
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
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average access time to the distant
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Watts Figure 5.6 Disk Power Model (
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exhibits little variation in power
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The memory model averaged about 9%
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efficiency rather than performance.
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through the application GUI. The nu
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1 data cache access rate dominates
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periods of disconnect, cache snoop
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5.3.4 CPU To test the extensibility
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Despite this, high accuracy of less
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Light activity yields higher precha
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5.3.8 Chipset The Chipset power mod
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applied to the GPU core logic, larg
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Chapter 6 Performance Effects of Dy
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can be considered as predictors whi
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Page 125 and 126: 6.1.5 Direct Performance Effects Si
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Page 169 and 170: Chapter 9 Conclusions and Future Wo
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Page 177 and 178: the 2005 ACM SIGMETRICS Internation
Page 179 and 180: [HaKe07] H. Hanson, S.W. Keckler, K
Page 181 and 182: [JoMa01] R. Joseph and M. Martonosi
Page 183 and 184: [LiBr05] Y. Li, D. Brooks, Z. Hu, a
Page 185 and 186: [Os06] Open Source Development Lab,
Page 187 and 188: [WaCh08] X. Wang and M. Chen. Clust
Page 189 and 190: [PiSh01] P. Pillai and K. G. Shin.
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